Merge branch 'YosysHQ:main' into master

tests/arch/run-test.sh

@@ -16,7 +16,7 @@ for arch in ../../techlibs/*; do
 			done
 		else
 			echo -n "Test $path ->"
-			iverilog -t null -I$arch $path
+			iverilog -t null -I$arch -g2005-sv $path
 			echo " ok"
 		fi
 	done

tests/cxxrtl/test_value_fuzz.cc

@@ -25,6 +25,11 @@ T rand_int(T min = std::numeric_limits<T>::min(), T max = std::numeric_limits<T>
 	return dist(generator);
 }
 
+int64_t sext(size_t bits, uint64_t value)
+{
+	return (int64_t)(value << (64 - bits)) >> (64 - bits);
+}
+
 struct BinaryOperationBase
 {
 	void tweak_input(uint64_t &a, uint64_t &b) {}
@@ -246,6 +251,106 @@ struct CtlzTest
 	}
 } ctlz;
 
+struct UdivTest : BinaryOperationBase
+{
+	UdivTest()
+	{
+		std::printf("Randomized tests for value::udivmod (div):\n");
+		test_binary_operation(*this);
+	}
+
+	uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b)
+	{
+		return a / b;
+	}
+
+	template<size_t Bits>
+	cxxrtl::value<Bits> testing_impl(cxxrtl::value<Bits> a, cxxrtl::value<Bits> b)
+	{
+		return std::get<0>(a.udivmod(b));
+	}
+
+	void tweak_input(uint64_t &, uint64_t &b)
+	{
+		if (b == 0) b = 1; // Avoid divide by zero
+	}
+} udiv;
+
+struct UmodTest : BinaryOperationBase
+{
+	UmodTest()
+	{
+		std::printf("Randomized tests for value::udivmod (mod):\n");
+		test_binary_operation(*this);
+	}
+
+	uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b)
+	{
+		return a % b;
+	}
+
+	template<size_t Bits>
+	cxxrtl::value<Bits> testing_impl(cxxrtl::value<Bits> a, cxxrtl::value<Bits> b)
+	{
+		return std::get<1>(a.udivmod(b));
+	}
+
+	void tweak_input(uint64_t &, uint64_t &b)
+	{
+		if (b == 0) b = 1; // Avoid divide by zero
+	}
+} umod;
+
+struct SdivTest : BinaryOperationBase
+{
+	SdivTest()
+	{
+		std::printf("Randomized tests for value::sdivmod (div):\n");
+		test_binary_operation(*this);
+	}
+
+	uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b)
+	{
+		return (uint64_t)(sext(bits, a) / sext(bits, b));
+	}
+
+	template<size_t Bits>
+	cxxrtl::value<Bits> testing_impl(cxxrtl::value<Bits> a, cxxrtl::value<Bits> b)
+	{
+		return std::get<0>(a.sdivmod(b));
+	}
+
+	void tweak_input(uint64_t &, uint64_t &b)
+	{
+		if (b == 0) b = 1; // Avoid divide by zero
+	}
+} sdiv;
+
+struct SmodTest : BinaryOperationBase
+{
+	SmodTest()
+	{
+		std::printf("Randomized tests for value::sdivmod (mod):\n");
+		test_binary_operation(*this);
+	}
+
+	uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b)
+	{
+		return (uint64_t)(sext(bits, a) % sext(bits, b));
+	}
+
+	template<size_t Bits>
+	cxxrtl::value<Bits> testing_impl(cxxrtl::value<Bits> a, cxxrtl::value<Bits> b)
+	{
+		return std::get<1>(a.sdivmod(b));
+	}
+
+	void tweak_input(uint64_t &, uint64_t &b)
+	{
+		if (b == 0) b = 1; // Avoid divide by zero
+	}
+} smod;
+
 int main()
 {
 }

tests/memlib/memlib_9b1B.v

@@ -1,4 +1,14 @@
-module RAM_9b1B (
+module RAM_9b1B 
+#(
+	parameter INIT = 0,
+	parameter OPTION_INIT = "UNDEFINED",
+	parameter PORT_R_WIDTH = 9,
+	parameter PORT_W_WIDTH = 9,
+	parameter PORT_R_CLK_POL = 0,
+	parameter PORT_W_CLK_POL = 0,
+	parameter PORT_W_WR_EN_WIDTH = 1
+)
+(
 	input PORT_R_CLK,
 	input [6:0] PORT_R_ADDR,
 	output reg [PORT_R_WIDTH-1:0] PORT_R_RD_DATA,
@@ -8,14 +18,6 @@ module RAM_9b1B (
 	input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA
 );
 
-parameter INIT = 0;
-parameter OPTION_INIT = "UNDEFINED";
-parameter PORT_R_WIDTH = 9;
-parameter PORT_W_WIDTH = 9;
-parameter PORT_R_CLK_POL = 0;
-parameter PORT_W_CLK_POL = 0;
-parameter PORT_W_WR_EN_WIDTH = 1;
-
 reg [8:0] mem [0:15];
 
 integer i;

tests/memlib/memlib_wren.v

@@ -1,4 +1,11 @@
-module RAM_WREN (
+module RAM_WREN #(
+	parameter ABITS=4,
+	parameter WIDTH=8,
+	parameter PORT_A_WR_EN_WIDTH=1,
+	parameter PORT_A_WR_BE_WIDTH=0,
+	parameter OPTION_BYTESIZE=WIDTH,
+	parameter WB=OPTION_BYTESIZE
+)(
 	input PORT_A_CLK,
 	input [ABITS-1:0] PORT_A_ADDR,
 	input [WIDTH-1:0] PORT_A_WR_DATA,
@@ -7,13 +14,6 @@ module RAM_WREN (
 	input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE
 );
 
-parameter ABITS=4;
-parameter WIDTH=8;
-parameter PORT_A_WR_EN_WIDTH=1;
-parameter PORT_A_WR_BE_WIDTH=0;
-parameter OPTION_BYTESIZE=WIDTH;
-parameter WB=OPTION_BYTESIZE;
-
 reg [WIDTH-1:0] mem [0:2**ABITS-1];
 
 integer i;

tests/memories/issue00335.v

@@ -2,13 +2,15 @@
 // expect-rd-ports 1
 // expect-rd-clk \clk
 
-module ram2 (input clk,
+module ram2 #(
+             parameter  SIZE = 5 // Address size
+          ) (input clk,
              input             sel,
              input             we, 
              input [SIZE-1:0]  adr, 
              input [63:0]      dat_i, 
              output reg [63:0] dat_o);
-   parameter  SIZE = 5; // Address size
+   
 
    reg [63:0] mem [0:(1 << SIZE)-1];
    integer    i;

tests/simple/.gitignore

@@ -1,2 +1,3 @@
 *.log
 *.out
+*.err

tests/techmap/kogge-stone.ys

@@ -0,0 +1 @@
+test_cell -s 1711533949 -n 10 -map +/techmap.v -map +/choices/kogge-stone.v $lcu

tests/verilog/.gitignore

@@ -1,6 +1,10 @@
 /*.log
 /*.out
+/*.err
 /run-test.mk
 /const_arst.v
 /const_sr.v
 /doubleslash.v
+/roundtrip_proc_1.v
+/roundtrip_proc_2.v
+/assign_to_reg.v

tests/verilog/assign_to_reg.ys

@@ -0,0 +1,22 @@
+# https://github.com/yosyshq/yosys/issues/2035
+
+read_ilang <<END
+module \top
+  wire width 1 input 0 \halfbrite
+  wire width 2 output 1 \r_on
+  process $1
+    assign \r_on [1:0] 2'00
+    assign \r_on [1:0] 2'11
+    switch \halfbrite [0]
+      case 1'1
+        assign \r_on [1] 1'0
+    end
+  end
+end
+END
+proc_prune
+write_verilog assign_to_reg.v
+design -reset
+
+logger -expect-no-warnings
+read_verilog assign_to_reg.v