mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00
Code Activity

Revisions (#4)

Browse source 
* area should be 1 for all LUTs

* clean up macros

* add log_assert to fail noisily when encountering oddly configured DFF

* clean help msg

* flatten set to true by default

* update

* merge mult tests

* remove redundant test

* move all dsp tests to single file and remove redundant tests

* update ram tests

* add more dff tests

* fix c++20 compile errors

* add option to dump verilog

* default to use abc9

* remove -abc9 option since its the default now

---------

Co-authored-by: tony <minchunlin@gmail.com>
This commit is contained in:
Tony Min 2024-07-08 10:57:16 -04:00 • committed by GitHub
parent 6fe0e00050
commit d41688f7d7
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
44 changed files with 435 additions and 1118 deletions
Download patch file Download diff file Expand all files Collapse all files

38
tests/arch/microchip/Registers.v
View file

@ -1,38 +0,0 @@
/*
ISC License
Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module Registers(
input clk,
input en,
input rst,
input D,
output reg Q
);
parameter LOAD_DATA = 1;
// active low async reset
always @(posedge clk, negedge rst) begin
if (rst == 0) begin
Q <= LOAD_DATA;
end else if(en) begin
Q <= D;
end
end
endmodule

24
tests/arch/microchip/Registers.ys
View file

@ -1,24 +0,0 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
# read verilog files
read_verilog Registers.v
synth_microchip -top Registers -abc9 -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CLKBUF
select -assert-none t:SLE t:CLKBUF %% t:* %D

34
tests/arch/microchip/carryout.v
View file

@ -1,34 +0,0 @@
/*
ISC License
Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module carryout (cout,out,a, b,c);
parameter n = 6;
parameter k = 2;
output reg [k*(n+1)-1:0] out;
output reg cout;
input [n:0] a;
input [n:0] b;
input [n-1:0] c;
always @(a,b,c)
begin
{cout,out} = a * b + c;
end
endmodule

22
tests/arch/microchip/carryout.ys
View file

@ -1,22 +0,0 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog carryout.v
synth_microchip -top carryout -abc9 -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

38
tests/arch/microchip/cascade.v
View file

@ -1,38 +0,0 @@
/*
ISC License
Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module cascade(
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output signed [11:0] out_P,
input signed [4:0] casA,
input signed [4:0] casB
);
wire signed [9:0] cascade;
// first dsp
assign cascade = casA * casB;
// second dsp
assign out_P = in_A * (in_B + in_D) + cascade;
endmodule

22
tests/arch/microchip/cascade.ys
View file

@ -1,22 +0,0 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog cascade.v
synth_microchip -top cascade -abc9 -family polarfire -noiopad
select -assert-count 2 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

76
tests/arch/microchip/dff.ys Normal file
View file

@ -0,0 +1,76 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
# active low async reset with enable
read_verilog <<EOT
module top(
input clk,
input en,
input rst,
input D,
output reg Q
);
always @(posedge clk, negedge rst) begin
if (rst == 0) begin
Q <= 1;
end else if(en) begin
Q <= D;
end
end
endmodule
EOT
synth_microchip -top top -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CLKBUF
select -assert-none t:SLE t:CLKBUF %% t:* %D
design -reset
read_verilog -D NO_INIT ../common/dffs.v
synth_microchip -top dff -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CLKBUF
select -assert-none t:SLE t:CLKBUF %% t:* %D
design -reset
read_verilog -D NO_INIT ../common/dffs.v
synth_microchip -top dffe -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CLKBUF
select -assert-none t:SLE t:CLKBUF %% t:* %D
design -reset
read_verilog -D NO_INIT ../common/adffs.v
synth_microchip -top adff -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CLKBUF
select -assert-count 1 t:CFG1
select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D
design -reset
read_verilog -D NO_INIT ../common/adffs.v
synth_microchip -top adffn -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CLKBUF
select -assert-none t:SLE t:CLKBUF %% t:* %D
design -reset
read_verilog -D NO_INIT ../common/adffs.v
synth_microchip -top dffs -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CLKBUF
select -assert-count 1 t:CFG1
select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D

2
tests/arch/microchip/dff_opt.ys
View file

@ -16,7 +16,7 @@
read_verilog dff_opt.v
synth_microchip -top dff_opt -abc9 -family polarfire -noiopad
synth_microchip -top dff_opt -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CFG4

211
tests/arch/microchip/dsp.ys Normal file
View file

@ -0,0 +1,211 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
# pre-adder
design -reset
read_verilog <<EOT
module pre_adder(
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output [11:0] out_Y
);
assign out_Y = in_A * (in_B + in_D);
endmodule
EOT
synth_microchip -top pre_adder -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D
# post-adder
design -reset
read_verilog <<EOT
module post_adder(
input signed[17:0] in_A,
input signed [17:0] in_B,
input signed [17:0] in_C,
output signed [35:0] out_Y
);
assign out_Y = (in_B*in_A)+in_C;
endmodule
EOT
synth_microchip -top post_adder -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D
# pre-adder + post-adder
design -reset
read_verilog <<EOT
module pre_post_adder(
input signed[5:0] in_A,
input signed [4:0] in_B,
input signed [11:0] in_C,
input signed [4:0] in_D,
output signed [12:0] out_Y
);
assign out_Y = ((in_D + in_B)*in_A)+in_C;
endmodule
EOT
synth_microchip -top pre_post_adder -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D
# multiply accumulate
design -reset
read_verilog <<EOT
module mac(
input clk,
input signed [4:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
input srst_P,
output reg signed [11:0] out_P
);
always@(posedge clk) begin
if (~srst_P) begin
out_P <= 12'h000;
end else begin
out_P <= in_A * (in_B + in_D) + out_P;
end
end
endmodule
EOT
synth_microchip -top mac -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D
# cascade
design -reset
read_verilog <<EOT
module cas(
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
input signed [4:0] casA,
input signed [4:0] casB,
output signed [11:0] out_P
);
wire signed [9:0] cascade;
assign cascade = casA * casB;
assign out_P = in_A * (in_B + in_D) + cascade;
endmodule
EOT
synth_microchip -top cas -family polarfire -noiopad
select -assert-count 2 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D
# carryout
design -reset
read_verilog <<EOT
module carryout (cout,out,a, b,c);
parameter n = 6;
parameter k = 2;
output reg [k*(n+1)-1:0] out;
output reg cout;
input [n:0] a;
input [n:0] b;
input [n-1:0] c;
always @(*)
begin
{cout,out} = a * b + c;
end
endmodule
EOT
synth_microchip -top carryout -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D
# pipeline registers
design -reset
read_verilog <<EOT
module pipeline(
input clk,
input srst_A,
input srst_B,
input srst_D,
input srst_P,
input arst_D,
input srst_C,
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_C,
input signed [4:0] in_D,
output reg [11:0] out_P
);
wire srst_A_N;
wire srst_B_N;
wire srst_C_N;
wire srst_D_N;
wire srst_P_N;
assign srst_A_N = ~srst_A;
assign srst_B_N = ~srst_B;
assign srst_C_N = ~srst_C;
assign srst_D_N = ~srst_D;
assign srst_P_N = ~srst_P;
reg signed [5:0] reg_A;
reg signed [4:0] reg_B;
reg signed [4:0] reg_C;
reg signed [4:0] reg_D;
always@(posedge clk) begin // sync reset A
// if (~srst_A_N) begin
if (srst_A_N) begin
reg_A = 6'b000000;
end else begin
reg_A = in_A;
end
end
always@(posedge clk) begin // sync reset B
if (srst_B_N) begin
reg_B = 5'b00000;
end else begin
reg_B = in_B;
end
end
always@(posedge clk, negedge arst_D) begin // async reset D
if (~arst_D) begin
reg_D = 5'b00000;
end else begin
reg_D = in_D;
end
end
always@(posedge clk) begin // sync reset C
if (srst_C_N) begin
reg_C = 5'b00000;
end else begin
reg_C = in_C;
end
end
// sync reset P
always@(posedge clk) begin
if (srst_P_N) begin
out_P = 12'h000;
end else begin
out_P = reg_A * (reg_B + reg_D) + reg_C;
end
end
endmodule
EOT
synth_microchip -top pipeline -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

30
tests/arch/microchip/full_dsp.v
View file

@ -1,30 +0,0 @@
/*
ISC License
Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module full_dsp(
input signed[5:0] in_A,
input signed [4:0] in_B,
input signed [11:0] in_C,
input signed [4:0] in_D,
output signed [12:0] out_Y
);
assign out_Y = ((in_D + in_B)*in_A)+in_C;
endmodule

22
tests/arch/microchip/full_dsp.ys
View file

@ -1,22 +0,0 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog full_dsp.v
synth_microchip -top full_dsp -abc9 -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

25
tests/arch/microchip/large_mult.v
View file

@ -1,25 +0,0 @@
/*
ISC License
Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module large_mult(
input signed [20:0] in1,
input signed [17:0] in2,
output signed [38:0] out1
);
assign out1 = in1 * in2;
endmodule

23
tests/arch/microchip/large_mult.ys
View file

@ -1,23 +0,0 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog large_mult.v
synth_microchip -top large_mult -abc9 -family polarfire -noiopad
select -assert-count 2 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

43
tests/arch/microchip/mac.v
View file

@ -1,43 +0,0 @@
/*
ISC License
Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module mac(
input clk,
input signed [4:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output reg signed [11:0] out_P,
input srst_P,
input signed [4:0] casA,
input signed [4:0] casB
);
// sync reset P
always@(posedge clk) begin
if (~srst_P) begin
out_P <= 12'h000;
end else begin
out_P <= in_A * (in_B + in_D) + out_P;
end
end
endmodule

24
tests/arch/microchip/mac.ys
View file

@ -1,24 +0,0 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
# read verilog files
read_verilog mac.v
# run the synth flow, specifies top module and additional parameters
synth_microchip -top mac -abc9 -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

51
tests/arch/microchip/mult.ys Normal file
View file

@ -0,0 +1,51 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
# regular unsigned multiply
read_verilog ../common/mul.v
chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
hierarchy -top top
proc
synth_microchip -family polarfire -noiopad
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D
# regular signed multiply
design -reset
read_verilog <<EOT
module signed_mult(
input signed [17:0] in_A,
input signed [17:0] in_B,
output signed [35:0] out_Y
);
assign out_Y = in_A * in_B;
endmodule
EOT
synth_microchip -top signed_mult -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D
# wide multiply
design -reset
read_verilog ../common/mul.v
chparam -set X_WIDTH 30 -set Y_WIDTH 16 -set A_WIDTH 46
hierarchy -top top
proc
synth_microchip -family polarfire -noiopad
cd top # Constrain all select calls below inside the top module
select -assert-count 2 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

30
tests/arch/microchip/postAdd_mult.v
View file

@ -1,30 +0,0 @@
/*
ISC License
Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module postAdd_mult(
input signed[17:0] in_A,
input signed [17:0] in_B,
input signed [17:0] in_C,
output signed [35:0] out_Y
);
assign out_Y = (in_B*in_A)+in_C;
endmodule

22
tests/arch/microchip/postAdd_mult.ys
View file

@ -1,22 +0,0 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog postAdd_mult.v
synth_microchip -top postAdd_mult -abc9 -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

32
tests/arch/microchip/post_adder.v
View file

@ -1,32 +0,0 @@
/*
ISC License
Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module post_adder(
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
input signed [11:0] in_C,
output [12:0] out_Y
);
assign out_Y = (in_D + in_B) * in_A + in_C;
endmodule

23
tests/arch/microchip/post_adder.ys
View file

@ -1,23 +0,0 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog post_adder.v
synth_microchip -top post_adder -abc9 -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

30
tests/arch/microchip/pre_adder_dsp.v
View file

@ -1,30 +0,0 @@
/*
ISC License
Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module pre_adder_dsp(
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output [11:0] out_Y
);
assign out_Y = in_A * (in_B + in_D);
endmodule

22
tests/arch/microchip/pre_adder_dsp.ys
View file

@ -1,22 +0,0 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog pre_adder_dsp.v
synth_microchip -top pre_adder_dsp -abc9 -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

12
tests/arch/microchip/ram_SDP.ys
View file

@ -15,10 +15,16 @@
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog ram_SDP.v
synth_microchip -top ram_SDP -abc9 -family polarfire -noiopad
synth_microchip -top ram_SDP -family polarfire -noiopad
select -assert-count 1 t:RAM1K20
select -assert-count 1 t:CFG1
select -assert-none t:RAM1K20 t:CFG1 %% t:* %D
# very similar to ram_SDP.v, except read enable is always active
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp
chparam -set DATA_WIDTH 32 -set ADDRESS_WIDTH 8
synth_microchip -top sync_ram_sdp -family polarfire -noiopad
select -assert-count 1 t:RAM1K20
select -assert-none t:RAM1K20 %% t:* %D

36
tests/arch/microchip/ram_TDP.v
View file

@ -27,30 +27,26 @@ reg [addr_width - 1 : 0] addra_reg, addrb_reg;
reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
always @ (posedge clka)
begin
addra_reg <= addra;
if(wea)
mem[addra] <= dataina;
begin
addra_reg <= addra;
if(wea) begin
mem[addra] <= dataina;
qa <= dataina;
end else begin
qa <= mem[addra];
end
always @ (posedge clkb)
begin
addrb_reg <= addrb;
if(web)
mem[addrb] <= datainb;
end
always @ (posedge clka)
begin
if(~wea)
qa <= mem[addra];
else qa <= dataina;
end
always @ (posedge clkb)
begin
if(~web)
qb <= mem[addrb];
else qb <= datainb;
addrb_reg <= addrb;
if(web) begin
mem[addrb] <= datainb;
qb <= datainb;
end else begin
qb <= mem[addrb];
end
end
endmodule

14
tests/arch/microchip/ram_TDP.ys
View file

@ -15,8 +15,16 @@
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog ram_TDP.v
synth_microchip -top ram_TDP -abc9 -family polarfire -noiopad -debug_memory
synth_microchip -top ram_TDP -family polarfire -noiopad
select -assert-count 1 t:RAM1K20
select -assert-none t:RAM1K20 %% t:* %D
# similar to ram_TDP.v, but different write mode and read_enable=~write_enable
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_tdp
chparam -set DATA_WIDTH 2 -set ADDRESS_WIDTH 10
synth_microchip -top sync_ram_tdp -family polarfire -noiopad
select -assert-count 1 t:RAM1K20
select -assert-count 2 t:CFG1
select -assert-none t:RAM1K20 t:CFG1 %% t:* %D

2
tests/arch/microchip/reduce.ys
View file

@ -16,7 +16,7 @@
read_verilog reduce.v
synth_microchip -top reduce -abc9 -family polarfire -noiopad
synth_microchip -top reduce -family polarfire -noiopad
select -assert-count 1 t:XOR8
select -assert-none t:XOR8 %% t:* %D

122
tests/arch/microchip/reg_c.v
View file

@ -1,122 +0,0 @@
/*
ISC License
Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module reg_c(
input clk,
// active high
input en_A,
input en_B,
input en_D,
input en_P,
// active low
input srst_A,
input srst_B,
input srst_D,
input srst_P,
// active low
input arst_D,
input srst_C,
input arst_C,
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_C,
input signed [4:0] in_D,
output reg [11:0] out_P
);
// MACC_PA takes active low resets
wire srst_A_N;
wire srst_B_N;
wire srst_C_N;
wire srst_D_N;
wire srst_P_N;
assign srst_A_N = ~srst_A;
assign srst_B_N = ~srst_B;
assign srst_C_N = ~srst_C;
assign srst_D_N = ~srst_D;
assign srst_P_N = ~srst_P;
// input reg
reg signed [5:0] reg_A;
reg signed [4:0] reg_B;
reg signed [4:0] reg_C;
reg signed [4:0] reg_D;
// sync reset A
always@(posedge clk) begin
// if (~srst_A_N) begin
if (srst_A_N) begin
reg_A = 6'b000000;
end else begin
reg_A = in_A;
end
end
// sync reset B
always@(posedge clk) begin
if (srst_B_N) begin
reg_B = 5'b00000;
end else begin
reg_B = in_B;
end
end
// async reset D
always@(posedge clk, negedge arst_D) begin
if (~arst_D) begin
reg_D = 5'b00000;
end else begin
reg_D = in_D;
end
end
// sync reset C
always@(posedge clk) begin
if (srst_C_N) begin
reg_C = 5'b00000;
end else begin
reg_C = in_C;
end
end
// sync reset P
always@(posedge clk) begin
if (srst_P_N) begin
out_P = 12'h000;
end else begin
out_P = reg_A * (reg_B + reg_D) + reg_C;
end
end
endmodule

22
tests/arch/microchip/reg_c.ys
View file

@ -1,22 +0,0 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog reg_c.v
synth_microchip -top reg_c -abc9 -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

97
tests/arch/microchip/reg_test.v
View file

@ -1,97 +0,0 @@
/*
ISC License
Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module reg_test(
input clk,
// active high
input en_A,
input en_B,
input en_D,
input en_P,
// active low
input srst_A,
input srst_B,
input srst_D,
input srst_P,
// active low
input arst_D,
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output reg [11:0] out_P
);
// MACC_PA takes active low resets
wire srst_A_N;
wire srst_B_N;
wire srst_D_N;
wire srst_P_N;
assign srst_A_N = ~srst_A;
assign srst_B_N = ~srst_B;
assign srst_D_N = ~srst_D;
assign srst_P_N = ~srst_P;
// input reg
reg signed [5:0] reg_A;
reg signed [4:0] reg_B;
reg signed [4:0] reg_D;
// sync reset A
always@(posedge clk) begin
if (srst_A_N) begin
reg_A = 6'b000000;
end else begin
reg_A = in_A;
end
end
// sync reset B
always@(posedge clk) begin
if (srst_B_N) begin
reg_B = 5'b00000;
end else begin
reg_B = in_B;
end
end
// async reset D
always@(posedge clk, negedge arst_D) begin
if (~arst_D) begin
reg_D = 5'b00000;
end else begin
reg_D = in_D;
end
end
// sync reset P
always@(posedge clk) begin
if (srst_P_N) begin
out_P = 12'h000;
end else begin
out_P = reg_A * (reg_B + reg_D);
end
end
endmodule

22
tests/arch/microchip/reg_test.ys
View file

@ -1,22 +0,0 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog reg_test.v
synth_microchip -top reg_test -abc9 -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

28
tests/arch/microchip/signed_mult.v
View file

@ -1,28 +0,0 @@
/*
ISC License
Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module signed_mult(
input signed [17:0] in_A,
input signed [17:0] in_B,
output signed [35:0] out_Y
);
assign out_Y = in_A * in_B;
endmodule

22
tests/arch/microchip/signed_mult.ys
View file

@ -1,22 +0,0 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog signed_mult.v
synth_microchip -top signed_mult -abc9 -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

37
tests/arch/microchip/simple_ram.v
View file

@ -1,37 +0,0 @@
/*
ISC License
Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module simple_ram (clk,wr,addr,din,dout);
input clk;
input [19:0] din;
input wr;
input [9:0] addr;
output [19:0] dout;
reg [9:0] addr_reg;
reg [19:0] mem [0:1023] ;
assign dout = mem[addr_reg];
always@(posedge clk) begin
addr_reg <= addr;
if(wr)
mem[addr]<= din;
end
endmodule

10
tests/arch/microchip/simple_ram.ys
View file

@ -14,9 +14,9 @@
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog simple_ram.v
synth_microchip -top simple_ram -abc9 -family polarfire -noiopad
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sp
chparam -set DATA_WIDTH 20 -set ADDRESS_WIDTH 10
synth_microchip -top sync_ram_sp -family polarfire -noiopad
select -assert-count 1 t:RAM1K20
select -assert-none t:RAM1K20 %% t:* %D
select -assert-none t:RAM1K20 %% t:* %D

28
tests/arch/microchip/unsigned_mult.v
View file

@ -1,28 +0,0 @@
/*
ISC License
Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module unsigned_mult(
input [10:0] in_A,
input signed [10:0] in_B,
output [21:0] out_Y
);
assign out_Y = in_A * in_B;
endmodule

22
tests/arch/microchip/unsigned_mult.ys
View file

@ -1,22 +0,0 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog unsigned_mult.v
synth_microchip -top unsigned_mult -abc9 -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

2
tests/arch/microchip/uram_ar.ys
View file

@ -16,7 +16,7 @@
read_verilog uram_ar.v
synth_microchip -top uram_ar -abc9 -family polarfire -noiopad
synth_microchip -top uram_ar -family polarfire -noiopad
select -assert-count 1 t:RAM64x12
select -assert-none t:RAM64x12 %% t:* %D

2
tests/arch/microchip/uram_sr.ys
View file

@ -16,7 +16,7 @@
read_verilog uram_sr.v
synth_microchip -top uram_sr -abc9 -family polarfire -noiopad
synth_microchip -top uram_sr -family polarfire -noiopad
select -assert-count 1 t:RAM64x12
select -assert-none t:RAM64x12 %% t:* %D

17
tests/arch/microchip/widemux.ys
View file

@ -16,7 +16,20 @@
read_verilog widemux.v
synth_microchip -top widemux -abc9 -family polarfire -noiopad
synth_microchip -top widemux -family polarfire -noiopad
select -assert-count 1 t:MX4
select -assert-none t:MX4 %% t:* %D
select -assert-none t:MX4 %% t:* %D
# RTL style is different here forming a different structure
read_verilog ../common/mux.v
design -save read
hierarchy -top mux4
proc
equiv_opt -assert -map +/microchip/cells_sim.v synth_microchip -top mux4 -family polarfire -noiopad
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 3 t:CFG3
select -assert-none t:CFG3 %% t:* %D