Updates for hiding verific

tests/verific/case.ys

@@ -1,12 +1,12 @@
-verific -cfg db_abstract_case_statement_synthesis 0
+import -cfg db_abstract_case_statement_synthesis 0
 read -sv case.sv
-verific -import top 
+import -import top 
 prep
 rename top gold
 
-verific -cfg db_abstract_case_statement_synthesis 1
+import -cfg db_abstract_case_statement_synthesis 1
 read -sv case.sv
-verific -import top 
+import -import top 
 prep
 rename top gate
 

tests/verific/clocking.ys

@@ -4,7 +4,7 @@ always @(*) assert(foo);
 endmodule
 EOT
 
-verific -import test
+import -import test
 prep
 
 select -assert-count 1 t:$assert

tests/verific/memory_semantics.ys

@@ -1,4 +1,4 @@
-verific -sv <<EOF
+import -sv <<EOF
 
 module top(clk);
 input wire clk;

tests/verific/range_case.ys

@@ -1,12 +1,12 @@
-verific -cfg db_abstract_case_statement_synthesis 0
+import -cfg db_abstract_case_statement_synthesis 0
 read -sv range_case.sv
-verific -import top 
+import -import top 
 proc
 rename top gold
 
-verific -cfg db_abstract_case_statement_synthesis 1
+import -cfg db_abstract_case_statement_synthesis 1
 read -sv range_case.sv
-verific -import top 
+import -import top 
 proc
 rename top gate
 

tests/verific/rom_case.ys.fail

@@ -1,4 +1,4 @@
-verific -sv <<EOF
+import -sv <<EOF
 module rom(input clk, input [2:0] addr, (* ram_style = "block" *) output reg [7:0] data);
 
 always @(posedge clk) begin
@@ -30,7 +30,7 @@ select -assert-count 1 t:RAM_BLOCK_SDP
 
 design -reset
 
-verific -vhdl <<EOF
+import -vhdl <<EOF
 library IEEE;
 use IEEE.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;