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Merge branch 'YosysHQ:main' into master

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This commit is contained in:
Akash Levy 2024-04-25 06:24:57 -07:00 • committed by GitHub
commit 45b723d6f3
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13 changed files with 69 additions and 33 deletions
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2
frontends/ast/genrtlil.cc
View file

@ -2224,7 +2224,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
else
input_error("FATAL.\n");
} else {
input_error("Unknown elabortoon system task '%s'.\n", str.c_str());
input_error("Unknown elaboration system task '%s'.\n", str.c_str());
}
} break;

2
kernel/driver.cc
View file

@ -356,7 +356,7 @@ int main(int argc, char **argv)
printf(" -V\n");
printf(" print version information and exit\n");
printf("\n");
printf("The option -S is an shortcut for calling the \"synth\" command, a default\n");
printf("The option -S is a shortcut for calling the \"synth\" command, a default\n");
printf("script for transforming the Verilog input to a gate-level netlist. For example:\n");
printf("\n");
printf(" yosys -o output.blif -S input.v\n");

2
passes/hierarchy/hierarchy.cc
View file

@ -47,7 +47,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
{
if (design->module(cell->type) != nullptr)
continue;
if (cell->type.begins_with("$__"))
if (cell->type.begins_with("$") && !cell->type.begins_with("$__"))
continue;
for (auto &pattern : celltypes)
if (patmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str()))

2
passes/pmgen/ice40_dsp.cc
View file

@ -289,7 +289,7 @@ struct Ice40DspPass : public Pass {
log("\n");
log("Pack input registers (A, B, {C,D}; with optional hold), pipeline registers\n");
log("({F,J,K,G}, H), output registers (O -- full 32-bits or lower 16-bits only; with\n");
log("optional hold), and post-adder into into the SB_MAC16 resource.\n");
log("optional hold), and post-adder into the SB_MAC16 resource.\n");
log("\n");
log("Multiply-accumulate operations using the post-adder with feedback on the {C,D}\n");
log("input will be folded into the DSP. In this scenario only, resetting the\n");

10
techlibs/anlogic/synth_anlogic.cc
View file

@ -169,12 +169,14 @@ struct SynthAnlogicPass : public ScriptPass
if (check_label("map_ram"))
{
std::string args = "";
if (nobram)
args += " -no-auto-block";
if (nolutram)
args += " -no-auto-distributed";
if (help_mode)
args += " [-no-auto-block] [-no-auto-distributed]";
else {
if (nobram)
args += " -no-auto-block";
if (nolutram)
args += " -no-auto-distributed";
}
run("memory_libmap -lib +/anlogic/lutrams.txt -lib +/anlogic/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
run("techmap -map +/anlogic/lutrams_map.v -map +/anlogic/brams_map.v");
}

10
techlibs/ecp5/synth_ecp5.cc
View file

@ -308,12 +308,14 @@ struct SynthEcp5Pass : public ScriptPass
if (check_label("map_ram"))
{
std::string args = "";
if (nobram)
args += " -no-auto-block";
if (nolutram)
args += " -no-auto-distributed";
if (help_mode)
args += " [-no-auto-block] [-no-auto-distributed]";
else {
if (nobram)
args += " -no-auto-block";
if (nolutram)
args += " -no-auto-distributed";
}
run("memory_libmap -lib +/ecp5/lutrams.txt -lib +/ecp5/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
run("techmap -map +/ecp5/lutrams_map.v -map +/ecp5/brams_map.v");
}

10
techlibs/efinix/synth_efinix.cc
View file

@ -161,9 +161,13 @@ struct SynthEfinixPass : public ScriptPass
if (check_label("map_ram"))
{
std::string args = "";
if (nobram)
args += " -no-auto-block";
run("memory_libmap -lib +/efinix/brams.txt" + args);
if (help_mode)
args += " [-no-auto-block]";
else {
if (nobram)
args += " -no-auto-block";
}
run("memory_libmap -lib +/efinix/brams.txt" + args, "(-no-auto-block if -nobram)");
run("techmap -map +/efinix/brams_map.v");
}

4
techlibs/fabulous/synth_fabulous.cc
View file

@ -320,7 +320,7 @@ struct SynthPass : public ScriptPass
run("opt_clean");
}
if (check_label("map_ram")) {
if (check_label("map_ram", "(unless -noregfile)")) {
// RegFile extraction
if (!noregfile) {
run("memory_libmap -lib +/fabulous/ram_regfile.txt");
@ -342,7 +342,7 @@ struct SynthPass : public ScriptPass
}
if (check_label("map_iopad", "(if -iopad)")) {
if (iopad) {
if (iopad || help_mode) {
run("opt -full");
run("iopadmap -bits -outpad $__FABULOUS_OBUF I:PAD -inpad $__FABULOUS_IBUF O:PAD "
"-toutpad IO_1_bidirectional_frame_config_pass ~T:I:PAD "

10
techlibs/gowin/synth_gowin.cc
View file

@ -230,12 +230,14 @@ struct SynthGowinPass : public ScriptPass
if (check_label("map_ram"))
{
std::string args = "";
if (nobram)
args += " -no-auto-block";
if (nolutram)
args += " -no-auto-distributed";
if (help_mode)
args += " [-no-auto-block] [-no-auto-distributed]";
else {
if (nobram)
args += " -no-auto-block";
if (nolutram)
args += " -no-auto-distributed";
}
run("memory_libmap -lib +/gowin/lutrams.txt -lib +/gowin/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
run("techmap -map +/gowin/lutrams_map.v -map +/gowin/brams_map.v");
}

10
techlibs/ice40/synth_ice40.cc
View file

@ -353,12 +353,14 @@ struct SynthIce40Pass : public ScriptPass
if (check_label("map_ram"))
{
std::string args = "";
if (!spram)
args += " -no-auto-huge";
if (nobram)
args += " -no-auto-block";
if (help_mode)
args += " [-no-auto-huge] [-no-auto-block]";
else {
if (!spram)
args += " -no-auto-huge";
if (nobram)
args += " -no-auto-block";
}
run("memory_libmap -lib +/ice40/brams.txt -lib +/ice40/spram.txt" + args, "(-no-auto-huge unless -spram, -no-auto-block if -nobram)");
run("techmap -map +/ice40/brams_map.v -map +/ice40/spram_map.v");
run("ice40_braminit");

10
techlibs/lattice/synth_lattice.cc
View file

@ -373,12 +373,14 @@ struct SynthLatticePass : public ScriptPass
if (check_label("map_ram"))
{
std::string args = "";
if (nobram)
args += " -no-auto-block";
if (nolutram)
args += " -no-auto-distributed";
if (help_mode)
args += " [-no-auto-block] [-no-auto-distributed]";
else {
if (nobram)
args += " -no-auto-block";
if (nolutram)
args += " -no-auto-distributed";
}
run("memory_libmap -lib +/lattice/lutrams.txt -lib +/lattice/brams" + brams_map + ".txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
run("techmap -map +/lattice/lutrams_map.v -map +/lattice/brams_map" + brams_map + ".v");
}

10
techlibs/nexus/synth_nexus.cc
View file

@ -300,12 +300,14 @@ struct SynthNexusPass : public ScriptPass
{
std::string args = "";
args += " -no-auto-huge";
if (nobram)
args += " -no-auto-block";
if (nolutram)
args += " -no-auto-distributed";
if (help_mode)
args += " [-no-auto-block] [-no-auto-distributed]";
else {
if (nobram)
args += " -no-auto-block";
if (nolutram)
args += " -no-auto-distributed";
}
run("memory_libmap -lib +/nexus/lutrams.txt -lib +/nexus/brams.txt -lib +/nexus/lrams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
run("techmap -map +/nexus/lutrams_map.v -map +/nexus/brams_map.v -map +/nexus/lrams_map.v");
}

20
tests/various/hierarchy_generate.ys Normal file
View file

@ -0,0 +1,20 @@
read_verilog -icells <<EOF
module top(input [2:0] a, input [2:0] b, output [2:0] y);
sub sub_i (.a(a[0]), .b(b[0]), .y(y[0]));
unknown_sub sub_ii (.a(a[1]), .b(b[1]), .y(y[1]));
$__dunder_sub sub_iii (.a(a[2]), .b(b[2]), .y(y[2]));
endmodule
module sub(input a, input b, output y);
assign y = a ^ b;
endmodule
EOF
hierarchy -generate unknown_sub i:a i:b o:y
hierarchy -generate $__dunder_sub i:a i:b o:y
hierarchy -generate $xor i:A i:B o:Y # this one is ignored
hierarchy -top top -check
check -assert