mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00
Code Activity

Merge pull request #4474 from tony-min-1/mchp

Browse source 
Add PolarFire FPGA support
This commit is contained in:
N. Engelhardt 2024-07-29 15:28:44 +02:00 • committed by GitHub
commit 9f869b265c
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
31 changed files with 4620 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

4
tests/arch/microchip/.gitignore vendored Normal file
View file

@ -0,0 +1,4 @@
*.log
/run-test.mk
*.vm

76
tests/arch/microchip/dff.ys Normal file
View file

@ -0,0 +1,76 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
# active low async reset with enable
read_verilog <<EOT
module top(
input clk,
input en,
input rst,
input D,
output reg Q
);
always @(posedge clk, negedge rst) begin
if (rst == 0) begin
Q <= 1;
end else if(en) begin
Q <= D;
end
end
endmodule
EOT
synth_microchip -top top -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CLKBUF
select -assert-none t:SLE t:CLKBUF %% t:* %D
design -reset
read_verilog -D NO_INIT ../common/dffs.v
synth_microchip -top dff -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CLKBUF
select -assert-none t:SLE t:CLKBUF %% t:* %D
design -reset
read_verilog -D NO_INIT ../common/dffs.v
synth_microchip -top dffe -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CLKBUF
select -assert-none t:SLE t:CLKBUF %% t:* %D
design -reset
read_verilog -D NO_INIT ../common/adffs.v
synth_microchip -top adff -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CLKBUF
select -assert-count 1 t:CFG1
select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D
design -reset
read_verilog -D NO_INIT ../common/adffs.v
synth_microchip -top adffn -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CLKBUF
select -assert-none t:SLE t:CLKBUF %% t:* %D
design -reset
read_verilog -D NO_INIT ../common/adffs.v
synth_microchip -top dffs -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CLKBUF
select -assert-count 1 t:CFG1
select -assert-none t:SLE t:CLKBUF t:CFG1 %% t:* %D

42
tests/arch/microchip/dff_opt.ys Normal file
View file

@ -0,0 +1,42 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
# reset can be merged into D LUT
read_verilog <<EOT
module dff_opt(
input clk,
input [1:0] D_comb,
input [1:0] EN_comb,
input [1:0] RST_comb,
output bar
);
reg foo;
assign bar = foo;
always@(posedge clk) begin
if (&RST_comb) begin
foo <= 0;
end else begin
foo <= &D_comb;
end
end
endmodule
EOT
synth_microchip -top dff_opt -family polarfire -noiopad
select -assert-count 1 t:SLE
select -assert-count 1 t:CFG4
select -assert-count 1 t:CLKBUF
select -assert-none t:SLE t:CFG4 t:CLKBUF %% t:* %D

211
tests/arch/microchip/dsp.ys Normal file
View file

@ -0,0 +1,211 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
# pre-adder
design -reset
read_verilog <<EOT
module pre_adder(
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
output [11:0] out_Y
);
assign out_Y = in_A * (in_B + in_D);
endmodule
EOT
synth_microchip -top pre_adder -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D
# post-adder
design -reset
read_verilog <<EOT
module post_adder(
input signed[17:0] in_A,
input signed [17:0] in_B,
input signed [17:0] in_C,
output signed [35:0] out_Y
);
assign out_Y = (in_B*in_A)+in_C;
endmodule
EOT
synth_microchip -top post_adder -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D
# pre-adder + post-adder
design -reset
read_verilog <<EOT
module pre_post_adder(
input signed[5:0] in_A,
input signed [4:0] in_B,
input signed [11:0] in_C,
input signed [4:0] in_D,
output signed [12:0] out_Y
);
assign out_Y = ((in_D + in_B)*in_A)+in_C;
endmodule
EOT
synth_microchip -top pre_post_adder -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D
# multiply accumulate
design -reset
read_verilog <<EOT
module mac(
input clk,
input signed [4:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
input srst_P,
output reg signed [11:0] out_P
);
always@(posedge clk) begin
if (~srst_P) begin
out_P <= 12'h000;
end else begin
out_P <= in_A * (in_B + in_D) + out_P;
end
end
endmodule
EOT
synth_microchip -top mac -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D
# cascade
design -reset
read_verilog <<EOT
module cas(
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_D,
input signed [4:0] casA,
input signed [4:0] casB,
output signed [11:0] out_P
);
wire signed [9:0] cascade;
assign cascade = casA * casB;
assign out_P = in_A * (in_B + in_D) + cascade;
endmodule
EOT
synth_microchip -top cas -family polarfire -noiopad
select -assert-count 2 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D
# carryout
design -reset
read_verilog <<EOT
module carryout (cout,out,a, b,c);
parameter n = 6;
parameter k = 2;
output reg [k*(n+1)-1:0] out;
output reg cout;
input [n:0] a;
input [n:0] b;
input [n-1:0] c;
always @(*)
begin
{cout,out} = a * b + c;
end
endmodule
EOT
synth_microchip -top carryout -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D
# pipeline registers
design -reset
read_verilog <<EOT
module pipeline(
input clk,
input srst_A,
input srst_B,
input srst_D,
input srst_P,
input arst_D,
input srst_C,
input signed [5:0] in_A,
input signed [4:0] in_B,
input signed [4:0] in_C,
input signed [4:0] in_D,
output reg [11:0] out_P
);
wire srst_A_N;
wire srst_B_N;
wire srst_C_N;
wire srst_D_N;
wire srst_P_N;
assign srst_A_N = ~srst_A;
assign srst_B_N = ~srst_B;
assign srst_C_N = ~srst_C;
assign srst_D_N = ~srst_D;
assign srst_P_N = ~srst_P;
reg signed [5:0] reg_A;
reg signed [4:0] reg_B;
reg signed [4:0] reg_C;
reg signed [4:0] reg_D;
always@(posedge clk) begin // sync reset A
// if (~srst_A_N) begin
if (srst_A_N) begin
reg_A = 6'b000000;
end else begin
reg_A = in_A;
end
end
always@(posedge clk) begin // sync reset B
if (srst_B_N) begin
reg_B = 5'b00000;
end else begin
reg_B = in_B;
end
end
always@(posedge clk, negedge arst_D) begin // async reset D
if (~arst_D) begin
reg_D = 5'b00000;
end else begin
reg_D = in_D;
end
end
always@(posedge clk) begin // sync reset C
if (srst_C_N) begin
reg_C = 5'b00000;
end else begin
reg_C = in_C;
end
end
// sync reset P
always@(posedge clk) begin
if (srst_P_N) begin
out_P = 12'h000;
end else begin
out_P = reg_A * (reg_B + reg_D) + reg_C;
end
end
endmodule
EOT
synth_microchip -top pipeline -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

51
tests/arch/microchip/mult.ys Normal file
View file

@ -0,0 +1,51 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
# regular unsigned multiply
read_verilog ../common/mul.v
chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
hierarchy -top top
proc
synth_microchip -family polarfire -noiopad
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D
# regular signed multiply
design -reset
read_verilog <<EOT
module signed_mult(
input signed [17:0] in_A,
input signed [17:0] in_B,
output signed [35:0] out_Y
);
assign out_Y = in_A * in_B;
endmodule
EOT
synth_microchip -top signed_mult -family polarfire -noiopad
select -assert-count 1 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D
# wide multiply
design -reset
read_verilog ../common/mul.v
chparam -set X_WIDTH 30 -set Y_WIDTH 16 -set A_WIDTH 46
hierarchy -top top
proc
synth_microchip -family polarfire -noiopad
cd top # Constrain all select calls below inside the top module
select -assert-count 2 t:MACC_PA
select -assert-none t:MACC_PA %% t:* %D

50
tests/arch/microchip/ram_SDP.ys Normal file
View file

@ -0,0 +1,50 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog <<EOT
module ram_SDP(data,waddr,we,clk,q);
parameter d_width = 32;
parameter addr_width = 8;
parameter mem_depth = 256;
input [d_width-1:0] data;
input [addr_width-1:0] waddr;
input we, clk;
output reg [d_width-1:0] q;
reg [d_width-1:0] mem [mem_depth-1:0];
always @(posedge clk) begin
if (we) begin
mem[waddr] <= data;
end else begin
q <= mem[waddr];
end
end
endmodule
EOT
synth_microchip -top ram_SDP -family polarfire -noiopad
select -assert-count 1 t:RAM1K20
select -assert-count 1 t:CFG1
select -assert-none t:RAM1K20 t:CFG1 %% t:* %D
# very similar to ram_SDP.v, except read enable is always active
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp
chparam -set DATA_WIDTH 32 -set ADDRESS_WIDTH 8
synth_microchip -top sync_ram_sdp -family polarfire -noiopad
select -assert-count 1 t:RAM1K20
select -assert-none t:RAM1K20 %% t:* %D

64
tests/arch/microchip/ram_TDP.ys Normal file
View file

@ -0,0 +1,64 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog <<EOT
module ram_TDP (clka,clkb,wea,addra,dataina,qa,web,addrb,datainb,qb);
parameter addr_width = 10;
parameter data_width = 2;
input clka,clkb,wea,web;
input [data_width - 1 : 0] dataina,datainb;
input [addr_width - 1 : 0] addra,addrb;
output reg [data_width - 1 : 0] qa,qb;
reg [addr_width - 1 : 0] addra_reg, addrb_reg;
reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
always @ (posedge clka)
begin
addra_reg <= addra;
if(wea) begin
mem[addra] <= dataina;
qa <= dataina;
end else begin
qa <= mem[addra];
end
end
always @ (posedge clkb)
begin
addrb_reg <= addrb;
if(web) begin
mem[addrb] <= datainb;
qb <= datainb;
end else begin
qb <= mem[addrb];
end
end
endmodule
EOT
synth_microchip -top ram_TDP -family polarfire -noiopad
select -assert-count 1 t:RAM1K20
select -assert-none t:RAM1K20 %% t:* %D
# similar to ram_TDP.v, but different write mode and read_enable=~write_enable
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_tdp
chparam -set DATA_WIDTH 2 -set ADDRESS_WIDTH 10
synth_microchip -top sync_ram_tdp -family polarfire -noiopad
select -assert-count 1 t:RAM1K20
select -assert-count 2 t:CFG1
select -assert-none t:RAM1K20 t:CFG1 %% t:* %D

28
tests/arch/microchip/reduce.ys Normal file
View file

@ -0,0 +1,28 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog <<EOT
module reduce(
input [7:0] data,
output Y
);
assign Y = ^data;
endmodule
EOT
synth_microchip -top reduce -family polarfire -noiopad
select -assert-count 1 t:XOR8
select -assert-none t:XOR8 %% t:* %D

4
tests/arch/microchip/run-test.sh Executable file
View file

@ -0,0 +1,4 @@
#!/usr/bin/env bash
set -eu
source ../../gen-tests-makefile.sh
run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"

22
tests/arch/microchip/simple_ram.ys Normal file
View file

@ -0,0 +1,22 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sp
chparam -set DATA_WIDTH 20 -set ADDRESS_WIDTH 10
synth_microchip -top sync_ram_sp -family polarfire -noiopad
select -assert-count 1 t:RAM1K20
select -assert-none t:RAM1K20 %% t:* %D

40
tests/arch/microchip/uram_ar.ys Normal file
View file

@ -0,0 +1,40 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog <<EOT
module uram_ar(data,waddr,we,clk,q);
parameter d_width = 12;
parameter addr_width = 2;
parameter mem_depth = 12;
input [d_width-1:0] data;
input [addr_width-1:0] waddr;
input we, clk;
output [d_width-1:0] q;
reg [d_width-1:0] mem [mem_depth-1:0];
assign q = mem[waddr];
always @(posedge clk) begin
if (we)
mem[waddr] <= data;
end
endmodule
EOT
synth_microchip -top uram_ar -family polarfire -noiopad
select -assert-count 1 t:RAM64x12
select -assert-none t:RAM64x12 %% t:* %D

45
tests/arch/microchip/uram_sr.ys Normal file
View file

@ -0,0 +1,45 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog <<EOT
module uram_sr(clk, wr, raddr, din, waddr, dout);
input clk;
input [11:0] din;
input wr;
input [5:0] waddr, raddr;
output [11:0] dout;
reg [5:0] raddr_reg;
reg [11:0] mem [0:63];
assign dout = mem[raddr_reg];
integer i;
initial begin
for (i = 0; i < 64; i = i + 1) begin
mem[i] = 12'hfff;
end
end
always@(posedge clk) begin
raddr_reg <= raddr;
if(wr)
mem[waddr]<= din;
end
endmodule
EOT
synth_microchip -top uram_sr -family polarfire -noiopad
select -assert-count 1 t:RAM64x12
select -assert-none t:RAM64x12 %% t:* %D

41
tests/arch/microchip/widemux.ys Normal file
View file

@ -0,0 +1,41 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
read_verilog <<EOT
module widemux(
input [3:0] data,
input S0,
input S1,
output Y
);
assign Y = S1 ? (S0 ? data[3] : data[1]) : (S0 ? data[2] : data[0]);
endmodule
EOT
synth_microchip -top widemux -family polarfire -noiopad
select -assert-count 1 t:MX4
select -assert-none t:MX4 %% t:* %D
# RTL style is different here forming a different structure
read_verilog ../common/mux.v
design -save read
hierarchy -top mux4
proc
equiv_opt -assert -map +/microchip/cells_sim.v synth_microchip -top mux4 -family polarfire -noiopad
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 3 t:CFG3
select -assert-none t:CFG3 %% t:* %D