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Add NX_CY

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Lofty 2024-03-01 11:10:52 +01:00 • committed by Miodrag Milanovic
parent b4e9bb0d85
commit b3f59c9820
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tests/arch/nanoxplore/add_sub.ys Normal file
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read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 2 t:NX_CY
select -assert-count 4 t:NX_LUT
select -assert-none t:NX_CY t:NX_LUT %% t:* %D