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peepopt: avoid shift-amount underflow

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phsauter 2024-06-13 22:40:12 +02:00
parent 62bff3a204
commit 34b5c6d062
2 changed files with 19 additions and 1 deletions
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15
tests/opt/bug4413.ys Normal file
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@ -0,0 +1,15 @@
read_verilog <<EOT
module top(
input wire shift,
input wire [4:0] data,
output wire out
);
wire [1:0] shift2 = shift - 1'b1;
assign out = data >> shift2;
endmodule
EOT
equiv_opt -assert peepopt