3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 09:05:32 +00:00
yosys/tests
2024-05-21 19:07:13 -07:00
..
aiger read_aiger: Fix incorrect read of binary Aiger without outputs 2024-04-29 14:06:58 +01:00
arch intel_alm: drop quartus support 2024-05-03 11:32:33 +01:00
asicworld
bind
blif
bram
cxxrtl cxxrtl: Fix sdivmod 2024-03-30 07:56:11 +00:00
errors
fmt
fsm
hana
liberty
lut
memfile
memlib Move parameters to module declaration 2024-04-08 12:44:37 +02:00
memories Move parameters to module declaration 2024-04-08 12:44:37 +02:00
opt Merge commit 2024-03-29 19:30:48 -07:00
opt_share
proc
realmath
rpc
sat
select
share
sim
simple write_verilog: don't assign to a reg. 2024-04-03 13:06:45 +02:00
simple_abc9
smv
sva tests/sva: Skip sva tests that use SBY until SBY is compatible again 2024-03-05 14:37:33 +01:00
svinterfaces
svtypes Modifications 2024-03-21 11:31:43 -07:00
techmap cellmatch: Rename the special design to $cellmatch 2024-05-03 16:42:41 +02:00
tools
unit
various Merge branch 'YosysHQ:main' into master 2024-04-25 06:24:57 -07:00
verific Updates for hiding verific 2024-04-09 07:16:22 -07:00
verilog write_verilog: don't assign to a reg. 2024-04-03 13:06:45 +02:00
vloghtb
xprop
gen-tests-makefile.sh