Add FFs and related tests

tests/arch/nanoxplore/adffs.ys

@@ -0,0 +1,46 @@
+read_verilog ../common/adffs.v
+design -save read
+
+hierarchy -top adff
+proc
+equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:NX_DFF
+
+select -assert-none t:NX_DFF %% t:* %D
+
+
+design -load read
+hierarchy -top adffn
+proc
+equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:NX_DFF
+select -assert-count 1 t:NX_LUT
+
+select -assert-none t:NX_DFF t:NX_LUT %% t:* %D
+
+
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:NX_DFF
+
+select -assert-none t:NX_DFF %% t:* %D
+
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:NX_DFF
+select -assert-count 1 t:NX_LUT
+
+select -assert-none t:NX_DFF t:NX_LUT %% t:* %D

tests/arch/nanoxplore/dffs.ys

@@ -0,0 +1,22 @@
+read_verilog ../common/dffs.v
+design -save read
+
+hierarchy -top dff
+proc
+equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:NX_DFF
+
+select -assert-none t:NX_DFF %% t:* %D
+
+design -load read
+hierarchy -top dffe
+proc
+equiv_opt -assert -async2sync -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:NX_DFF
+select -assert-count 1 t:NX_LUT
+
+select -assert-none t:NX_DFF t:NX_LUT %% t:* %D

tests/arch/nanoxplore/fsm.ys

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+read_verilog ../common/fsm.v
+hierarchy -top fsm
+proc
+flatten
+
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v synth_nanoxplore
+async2sync
+miter -equiv -make_assert -flatten gold gate miter
+sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd fsm # Constrain all select calls below inside the top module
+
+select -assert-count 6 t:NX_DFF
+select -assert-count 13 t:NX_LUT
+select -assert-none t:NX_DFF t:NX_LUT %% t:* %D

tests/arch/nanoxplore/latches.ys

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+read_verilog ../common/latches.v
+design -save read
+
+hierarchy -top latchp
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_nanoxplore
+cd latchp # Constrain all select calls below inside the top module
+select -assert-count 1 t:NX_DFF
+
+select -assert-none t:NX_DFF %% t:* %D
+
+
+design -load read
+hierarchy -top latchn
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_nanoxplore
+cd latchn # Constrain all select calls below inside the top module
+select -assert-count 1 t:NX_LUT
+select -assert-count 1 t:NX_DFF
+
+select -assert-none t:NX_LUT t:NX_DFF %% t:* %D
+
+
+design -load read
+hierarchy -top latchsr
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_nanoxplore
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 2 t:NX_LUT
+select -assert-count 1 t:NX_DFF
+
+select -assert-none t:NX_LUT t:NX_DFF %% t:* %D

tests/arch/nanoxplore/shifter.ys

@@ -0,0 +1,10 @@
+read_verilog ../common/shifter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -async2sync -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 8  t:NX_DFF
+select -assert-none t:NX_DFF %% t:* %D