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Merge pull request #4323 from YosysHQ/tests_update

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Tests update for latest more strict iverilog
This commit is contained in:
N. Engelhardt 2024-04-08 15:10:59 +02:00 • committed by GitHub
commit 8e8885e1cc
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5 changed files with 49 additions and 44 deletions
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2
tests/arch/run-test.sh
View file

@ -16,7 +16,7 @@ for arch in ../../techlibs/*; do
done
else
echo -n "Test $path ->"
iverilog -t null -I$arch $path
iverilog -t null -I$arch -g2005-sv $path
echo " ok"
fi
done

20
tests/memlib/memlib_9b1B.v
View file

@ -1,4 +1,14 @@
module RAM_9b1B (
module RAM_9b1B
#(
parameter INIT = 0,
parameter OPTION_INIT = "UNDEFINED",
parameter PORT_R_WIDTH = 9,
parameter PORT_W_WIDTH = 9,
parameter PORT_R_CLK_POL = 0,
parameter PORT_W_CLK_POL = 0,
parameter PORT_W_WR_EN_WIDTH = 1
)
(
input PORT_R_CLK,
input [6:0] PORT_R_ADDR,
output reg [PORT_R_WIDTH-1:0] PORT_R_RD_DATA,
@ -8,14 +18,6 @@ module RAM_9b1B (
input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA
);
parameter INIT = 0;
parameter OPTION_INIT = "UNDEFINED";
parameter PORT_R_WIDTH = 9;
parameter PORT_W_WIDTH = 9;
parameter PORT_R_CLK_POL = 0;
parameter PORT_W_CLK_POL = 0;
parameter PORT_W_WR_EN_WIDTH = 1;
reg [8:0] mem [0:15];
integer i;

16
tests/memlib/memlib_wren.v
View file

@ -1,4 +1,11 @@
module RAM_WREN (
module RAM_WREN #(
parameter ABITS=4,
parameter WIDTH=8,
parameter PORT_A_WR_EN_WIDTH=1,
parameter PORT_A_WR_BE_WIDTH=0,
parameter OPTION_BYTESIZE=WIDTH,
parameter WB=OPTION_BYTESIZE
)(
input PORT_A_CLK,
input [ABITS-1:0] PORT_A_ADDR,
input [WIDTH-1:0] PORT_A_WR_DATA,
@ -7,13 +14,6 @@ module RAM_WREN (
input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE
);
parameter ABITS=4;
parameter WIDTH=8;
parameter PORT_A_WR_EN_WIDTH=1;
parameter PORT_A_WR_BE_WIDTH=0;
parameter OPTION_BYTESIZE=WIDTH;
parameter WB=OPTION_BYTESIZE;
reg [WIDTH-1:0] mem [0:2**ABITS-1];
integer i;

6
tests/memories/issue00335.v
View file

@ -2,13 +2,15 @@
// expect-rd-ports 1
// expect-rd-clk \clk
module ram2 (input clk,
module ram2 #(
parameter SIZE = 5 // Address size
) (input clk,
input sel,
input we,
input [SIZE-1:0] adr,
input [63:0] dat_i,
output reg [63:0] dat_o);
parameter SIZE = 5; // Address size
reg [63:0] mem [0:(1 << SIZE)-1];
integer i;