Akash Levy
8b93aa10cb
Add leakage power unit support
2024-05-29 23:43:47 -07:00
Akash Levy
a55a4d461e
Infer wide operators pre elaboration (post does not work as well!)
2024-05-28 04:39:29 -07:00
Akash Levy
4062825a9e
Disable Liberty support, add blackbox Verilog module, and add attribute parsing into Yosys Liberty parser
2024-05-28 01:47:46 -07:00
Akash Levy
b90c20cd14
Update Verific, add opt to hierarchy pass, make opt run a bunch of Verific optimizations, update some Verific runtime flags
2024-05-27 21:56:08 -07:00
Akash Levy
a98fcbd48b
Revert Verific flags
2024-05-25 23:21:31 -07:00
Akash Levy
60ce37c2bd
Don't reenable verific, move to c_cpp_properties.json in .vscode
2024-05-24 01:49:54 -07:00
Akash Levy
22bdf4035a
Verific to handle all RAMs
2024-05-24 01:08:37 -07:00
Akash Levy
6300c491ea
Update Yosys runtime flags for Verific to remove multi-port memory support
2024-05-24 00:26:37 -07:00
Akash Levy
66eabb1d2c
Define SYNTH and OVL_SVA by default
2024-05-23 21:05:57 -07:00
Akash Levy
187737b86a
Don't adjust naming on imported cells. Add $ for each pass
2024-05-19 15:02:40 -07:00
Akash Levy
60e598b9c8
Define SYNTHESIS earlier and in both, support ignored module specification
2024-05-17 04:46:28 -07:00
Akash Levy
375f73bbce
Update for Amba support
2024-05-15 15:37:14 -07:00
Akash Levy
ed42470d45
Move ignore translate up here and update verificc
2024-05-14 16:02:33 -07:00
Akash Levy
81b542fd31
Updated to support Amba comments and .h files
2024-05-14 13:25:43 -07:00
Akash Levy
667c3375e8
Macro defines don't pass or succeed the same way
2024-05-13 15:53:54 -07:00
Akash Levy
fb182d10d6
Update formats to include .svh
2024-05-13 00:00:49 -07:00
Akash Levy
ba5b12ae0c
Don't include source in name
2024-05-11 23:14:39 -07:00
Akash Levy
36f9c50c03
Add mode for nested capital F file
2024-05-11 12:53:33 -07:00
Akash Levy
a7e1dcef12
Move register file to after registering directories, also rename to AUTO-DISCOVER
2024-05-10 12:44:36 -07:00
Akash Levy
fb55287a3b
Add SVP extension, log auto-discovery, support gzip in verific
2024-05-10 11:09:22 -07:00
Akash Levy
c7f66737aa
Fix Yosys to allow SV again
2024-05-09 06:36:02 -07:00
Akash Levy
da8c1955af
Updates from YosysHQ
2024-05-09 05:10:44 -07:00
Akash Levy
8841cc4d76
Copy all info from .f file to hdl_file_sort for better auto-discovery
2024-05-09 04:54:57 -07:00
Akash Levy
b5af9b9a8a
Fix SystemVerilog support for .v files
2024-05-09 04:54:00 -07:00
Miodrag Milanović
1a54e8d47b
Merge pull request #4379 from QuantamHD/fix_verific
...
frontend: Fixes verific import around range order
2024-05-09 11:52:34 +02:00
Ethan Mahintorabi
82a4a87c97
Fixes error with vector indicies of the form [2:7] [-12:7]
...
Make sure that we correctly adjust the value to align it to a zero
indexed list with lsb = 0
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-05-08 20:29:47 +00:00
Akash Levy
47b6738124
Add -auto_discover to import
2024-05-08 04:21:30 -07:00
Akash Levy
2e21078a83
Merge branch 'YosysHQ:main' into master
2024-05-07 18:21:19 -07:00
Ethan Mahintorabi
c039da2ec1
renames variables for more code clairty
...
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-05-08 01:09:52 +00:00
Ethan Mahintorabi
a2c1b268d9
frontend: Fixes verific import around range order
...
Test Case
```
module packed_dimensions_range_ordering (
input wire [0:4-1] in,
output wire [4-1:0] out
);
assign out = in;
endmodule : packed_dimensions_range_ordering
module instanciates_packed_dimensions_range_ordering (
input wire [4-1:0] in,
output wire [4-1:0] out
);
packed_dimensions_range_ordering U0 (
.in (in),
.out(out)
);
endmodule : instanciates_packed_dimensions_range_ordering
```
```
// with verific, does not pass formal
module instanciates_packed_dimensions_range_ordering(in, out);
input [3:0] in;
wire [3:0] in;
output [3:0] out;
wire [3:0] out;
assign out = { in[0], in[1], in[2], in[3] };
endmodule
// with surelog, passes formal
module instanciates_packed_dimensions_range_ordering(in, out);
input [3:0] in;
wire [3:0] in;
output [3:0] out;
wire [3:0] out;
assign out = in;
endmodule
```
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-05-08 01:00:06 +00:00
Krystine Sherwin
df95ea824b
read_verilog: Add missing defaults for flags
...
Fix for YosysHQ/sby#103
2024-05-07 20:25:36 +02:00
Akash Levy
8c330c0e4b
Merge branch 'YosysHQ:main' into master
2024-04-29 22:22:47 -07:00
George Rennie
4e6deb53b6
read_aiger: Fix incorrect read of binary Aiger without outputs
...
* Also makes all ascii parsing finish reading lines and adds a small
test
2024-04-29 14:06:58 +01:00
Akash Levy
45b723d6f3
Merge branch 'YosysHQ:main' into master
2024-04-25 06:24:57 -07:00
KrystalDelusion
c3ae33da33
Merge pull request #4285 from YosysHQ/typo_fixup
...
Typo fixing
2024-04-25 09:54:48 +12:00
Akash Levy
3945e6ecff
Merge branch 'YosysHQ:main' into master
2024-04-16 10:59:45 -07:00
Miodrag Milanovic
af94123730
verific: expose library name as module attribute
2024-04-15 17:01:07 +02:00
Akash Levy
6a3bb58d5d
Updates from yosys
2024-04-14 18:53:44 -07:00
N. Engelhardt
3d5e23e585
Merge pull request #4302 from YosysHQ/vhdl_2019
...
Verific support for VHDL 2019
2024-04-09 18:25:05 +02:00
N. Engelhardt
18afa36acd
Merge pull request #4273 from YosysHQ/vhdl_params
...
verific: Improve import VHDL constants
2024-04-09 18:01:41 +02:00
Akash Levy
29e9d3ea92
Updates for hiding verific
2024-04-09 07:16:22 -07:00
akash
840cdb415b
Update Verific, add to gitmodules, remove unused/GPL features from Makefile
2024-04-08 12:36:08 -07:00
Akash Levy
e3f633fae6
Merge branch 'YosysHQ:main' into master
2024-04-08 12:26:40 -07:00
Catherine
a5441bc00c
fmt: FmtPart::{STRING→LITERAL},{CHARACTER→STRING}.
...
Before this commit, the `STRING` variant inserted a literal string;
the `CHARACTER` variant inserted a string. This commit renames them
to `LITERAL` and `STRING` respectively.
2024-04-02 12:13:22 +02:00
Miodrag Milanovic
f536de0e0e
Verific support for VHDL 2019
2024-03-28 13:21:55 +01:00
Akash Levy
dd35d2da23
Modifications
2024-03-21 11:31:43 -07:00
Miodrag Milanovic
4367e176fb
code split and cleanup
2024-03-19 09:15:04 +01:00
Miodrag Milanovic
9eebc80170
handle standard types
2024-03-18 10:35:01 +01:00
Krystine Sherwin
3eeefd23e3
Typo fixup(s)
2024-03-18 11:09:23 +13:00
Miodrag Milanovic
7c09fa572e
real number handling and default to string
2024-03-14 10:37:56 +01:00
