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	frontend: Fixes verific import around range order
Test Case
```
module packed_dimensions_range_ordering (
    input  wire [0:4-1] in,
    output wire [4-1:0] out
);
  assign out = in;
endmodule : packed_dimensions_range_ordering
module instanciates_packed_dimensions_range_ordering (
    input  wire [4-1:0] in,
    output wire [4-1:0] out
);
  packed_dimensions_range_ordering U0 (
      .in (in),
      .out(out)
  );
endmodule : instanciates_packed_dimensions_range_ordering
```
```
// with verific, does not pass formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;
  assign out = { in[0], in[1], in[2], in[3] };
endmodule
// with surelog, passes formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;
  assign out = in;
endmodule
```
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
			
			
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					 1 changed files with 10 additions and 2 deletions
				
			
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			@ -2156,8 +2156,16 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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			int port_offset = 0;
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			if (pr->GetPort()->Bus()) {
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				port_name = pr->GetPort()->Bus()->Name();
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				port_offset = pr->GetPort()->Bus()->IndexOf(pr->GetPort()) -
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						min(pr->GetPort()->Bus()->LeftIndex(), pr->GetPort()->Bus()->RightIndex());
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				int msb = pr->GetPort()->Bus()->LeftIndex();
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				int lsb = pr->GetPort()->Bus()->RightIndex();
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				int index_of_port = pr->GetPort()->Bus()->IndexOf(pr->GetPort());
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				port_offset =  index_of_port - min(msb, lsb);
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				// In cases where the msb order is flipped we need to make sure
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				// that the indicies match LSB = 0 order to match the std::vector
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				// to SigSpec LSB = 0 precondition.
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				if (lsb > msb) {
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					port_offset = abs(port_offset - lsb);
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				}
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			}
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			IdString port_name_id = RTLIL::escape_id(port_name);
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			auto &sigvec = cell_port_conns[port_name_id];
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