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Define SYNTHESIS earlier and in both, support ignored module specification

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This commit is contained in:
Akash Levy 2024-05-17 04:46:28 -07:00
parent a94cd0b3d8
commit 60e598b9c8
2 changed files with 12 additions and 6 deletions
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16
frontends/verific/verific.cc
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@ -3394,8 +3394,13 @@ struct VerificPass : public Pass {
unsigned verilog_mode = veri_file::SYSTEM_VERILOG;
const char* arg = args[argidx].c_str();
// Define macros
hdl_file_sort::DefineMacro("SYNTHESIS");
veri_file::DefineMacro("SYNTHESIS");
// Ignore translate_off statements
hdl_file_sort::SetIgnoreTranslateOff(0);
veri_file::SetIgnoreTranslateOff(0);
// Treat .v as SystemVerilog too (overriding default behavior to treat it as VERILOG_2000)
hdl_file_sort::RemoveFileExt(".v");
@ -3468,6 +3473,12 @@ struct VerificPass : public Pass {
log("AUTO-DISCOVER: registered file %s from .f file processing\n", file_name);
}
delete file_names;
} else if (args[argidx] == "-i") {
const char *ignore_module = args[++argidx].c_str();
log("AUTO-DISCOVER: ignoring module %s\n", ignore_module);
veri_file::AddToIgnoredModuleNames(ignore_module);
veri_file::AddToIgnoredParsedModuleNames(ignore_module);
hdl_file_sort::RegisterIgnoreUnitName(ignore_module);
} else {
veri_file::AddIncludeDir(args[argidx].c_str());
if (!hdl_file_sort::RegisterDir(args[argidx].c_str())) {
@ -3478,11 +3489,6 @@ struct VerificPass : public Pass {
}
}
// Define macros
hdl_file_sort::DefineMacro("YOSYS");
hdl_file_sort::DefineMacro("VERIFIC");
hdl_file_sort::DefineMacro("SYNTHESIS");
// Analyze discovered/sorted files
if (!analyze_function(veri_file::MFCU)) {
verific_error_msg.clear();

2
verific

@ -1 +1 @@
Subproject commit 28f79dbcfa0d0a96a9fe02f7ed075df7f48682a6
Subproject commit 9f13ecc2e1f265ee03a3548d11c68e290e7ec4bf