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Merge branch 'YosysHQ:main' into master

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Akash Levy 2024-04-16 10:59:45 -07:00 • committed by GitHub
commit 3945e6ecff
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9 changed files with 111 additions and 22 deletions
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frontends/verific/verific.cc
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@ -1432,6 +1432,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
}
import_attributes(module->attributes, nl, nl);
module->set_string_attribute(ID::hdlname, nl->CellBaseName());
module->set_string_attribute(ID(library), nl->Owner()->Owner()->Name());
#ifdef VERIFIC_VHDL_SUPPORT
if (nl->IsFromVhdl()) {
NameSpace name_space(0);