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Merge branch 'YosysHQ:main' into master

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Akash Levy 2024-05-07 18:21:19 -07:00 • committed by GitHub
commit 2e21078a83
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6 changed files with 297 additions and 100 deletions
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frontends/verilog/verilog_frontend.cc
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@ -270,8 +270,11 @@ struct VerilogFrontend : public Frontend {
frontend_verilog_yydebug = false;
sv_mode = false;
formal_mode = false;
noassert_mode = false;
noassume_mode = false;
norestrict_mode = false;
assume_asserts_mode = false;
assert_assumes_mode = false;
lib_mode = false;
specify_mode = false;
default_nettype_wire = true;