mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 17:15:33 +00:00
Code Activity

Move ignore translate up here and update verificc

Browse source
This commit is contained in:
Akash Levy 2024-05-14 16:02:33 -07:00
parent 81b542fd31
commit ed42470d45
1 changed files with 3 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

3
frontends/verific/verific.cc
View file

@ -3394,6 +3394,9 @@ struct VerificPass : public Pass {
unsigned verilog_mode = veri_file::SYSTEM_VERILOG;
const char* arg = args[argidx].c_str();
// Ignore translate_off statements
hdl_file_sort::SetIgnoreTranslateOff(0);
// Treat .v as SystemVerilog too (overriding default behavior to treat it as VERILOG_2000)
hdl_file_sort::RemoveFileExt(".v");
hdl_file_sort::AddFileExtMode(".v", veri_file::SYSTEM_VERILOG);