Modifications

Makefile

@@ -1,6 +1,6 @@
 
-CONFIG := clang
-# CONFIG := gcc
+# CONFIG := clang
+CONFIG := gcc
 # CONFIG := afl-gcc
 # CONFIG := emcc
 # CONFIG := wasi
@@ -16,11 +16,11 @@ ENABLE_PLUGINS := 1
 ENABLE_READLINE := 1
 ENABLE_EDITLINE := 0
 ENABLE_GHDL := 0
-ENABLE_VERIFIC := 0
-ENABLE_VERIFIC_EDIF := 0
-ENABLE_VERIFIC_LIBERTY := 0
-DISABLE_VERIFIC_EXTENSIONS := 0
-DISABLE_VERIFIC_VHDL := 0
+ENABLE_VERIFIC := 1
+ENABLE_VERIFIC_EDIF := 1
+ENABLE_VERIFIC_LIBERTY := 1
+DISABLE_VERIFIC_EXTENSIONS := 1
+DISABLE_VERIFIC_VHDL := 1
 ENABLE_COVER := 1
 ENABLE_LIBYOSYS := 0
 ENABLE_ZLIB := 1
@@ -515,7 +515,7 @@ endif
 LIBS_VERIFIC =
 ifeq ($(ENABLE_VERIFIC),1)
 VERIFIC_DIR ?= /usr/local/src/verific_lib
-VERIFIC_COMPONENTS ?= verilog database util containers hier_tree
+VERIFIC_COMPONENTS ?= verilog database util containers hier_tree sdf
 ifneq ($(DISABLE_VERIFIC_VHDL),1)
 VERIFIC_COMPONENTS += vhdl
 CXXFLAGS += -DVERIFIC_VHDL_SUPPORT

frontends/verific/verific.cc

@@ -71,13 +71,13 @@ USING_YOSYS_NAMESPACE
 #include "VerificExtensions.h"
 #endif
 
-#ifndef YOSYSHQ_VERIFIC_API_VERSION
-#  error "Only YosysHQ flavored Verific is supported. Please contact office@yosyshq.com for commercial support for Yosys+Verific."
-#endif
+//#ifndef YOSYSHQ_VERIFIC_API_VERSION
+//#  error "Only YosysHQ flavored Verific is supported. Please contact office@yosyshq.com for commercial support for Yosys+Verific."
+//#endif
 
-#if YOSYSHQ_VERIFIC_API_VERSION < 20230901
-#  error "Please update your version of YosysHQ flavored Verific."
-#endif
+//#if YOSYSHQ_VERIFIC_API_VERSION < 20230901
+//#  error "Please update your version of YosysHQ flavored Verific."
+//#endif
 
 #ifdef __clang__
 #pragma clang diagnostic pop
@@ -1127,6 +1127,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 		return true;
 	}
 
+	/*
 	if (inst->Type() == OPER_YOSYSHQ_SET_TAG)
 	{
 		RTLIL::SigSpec sig_expr = operatorInport(inst, "expr");
@@ -1163,6 +1164,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 		module->connect(operatorOutput(inst),module->FutureFF(new_verific_id(inst), operatorInput(inst)));
 		return true;
 	}
+	*/
 
 	#undef IN
 	#undef IN1
@@ -1927,7 +1929,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 				continue;
 		}
 
-		if (inst->Type() == PRIM_YOSYSHQ_INITSTATE)
+		/* if (inst->Type() == PRIM_YOSYSHQ_INITSTATE)
 		{
 			if (verific_verbose)
 				log("   adding YosysHQ init state\n");
@@ -1938,6 +1940,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 			if (!mode_keep)
 				continue;
 		}
+		*/
 
 		if (!mode_keep && verific_sva_prims.count(inst->Type())) {
 			if (verific_verbose)