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read_verilog: Add missing defaults for flags

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Fix for YosysHQ/sby#103
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Krystine Sherwin 2024-04-06 14:24:34 +13:00 committed by N. Engelhardt
parent 71f2540cd8
commit df95ea824b
1 changed files with 3 additions and 0 deletions
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frontends/verilog/verilog_frontend.cc
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@ -270,8 +270,11 @@ struct VerilogFrontend : public Frontend {
frontend_verilog_yydebug = false;
sv_mode = false;
formal_mode = false;
noassert_mode = false;
noassume_mode = false;
norestrict_mode = false;
assume_asserts_mode = false;
assert_assumes_mode = false;
lib_mode = false;
specify_mode = false;
default_nettype_wire = true;