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Disable Liberty support, add blackbox Verilog module, and add attribute parsing into Yosys Liberty parser

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This commit is contained in:
Akash Levy 2024-05-28 01:47:46 -07:00
parent b90c20cd14
commit 4062825a9e
2 changed files with 9 additions and 0 deletions
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6
frontends/liberty/liberty.cc
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@ -591,6 +591,12 @@ struct LibertyFrontend : public Frontend {
for (auto node : cell->children)
{
if (node->id == "area")
module->attributes["\\area"] = node->value;
if (node->id == "cell_leakage_power")
module->attributes["\\LeakagePower"] = node->value;
if (node->id == "pin" && node->args.size() == 1) {
LibertyAst *dir = node->find("direction");
if (!dir || (dir->value != "input" && dir->value != "output" && dir->value != "inout" && dir->value != "internal"))

3
frontends/verific/verific.cc
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@ -3459,6 +3459,9 @@ struct VerificPass : public Pass {
veri_file::AddFileExtMode(".svh", veri_file::SYSTEM_VERILOG);
veri_file::AddFileExtMode(".svp", veri_file::SYSTEM_VERILOG);
veri_file::AddFileExtMode(".h", veri_file::SYSTEM_VERILOG);
// Add blackbox modules
veri_file::AddVFile("preqorsor/data/blackboxes.v");
// Select analyze function
auto analyze_function = (args[argidx] == "-auto_discover") ? hdl_file_sort::AnalyzeDiscoveredFiles : hdl_file_sort::AnalyzeSortedFiles;