1642 commits

Author	SHA1	Message	Date
Akash Levy	e360511339	Merge branch 'YosysHQ:main' into main	2025-03-10 14:21:49 -07:00
Alain Dargelas	268459e00a	write_verilog -srcattronly option	2025-03-10 10:15:24 -07:00
Alain Dargelas	1b1882fe56	write_verilog -srcattronly option	2025-03-10 09:29:48 -07:00
Alain Dargelas	e35032f2f6	write_verilog -onlysrcattr option	2025-03-10 09:27:27 -07:00
N. Engelhardt	c74df780b7	Merge pull request #4884 from YosysHQ/docs-preview-functional_tutorial ... Docs: More on FunctionalIR	2025-03-10 15:05:55 +00:00
Krystine Sherwin	fa2d45a922	smtr: Refactor write back into _eval and _initial ... Easier for comparisons, and the structure still works. (I don't remember why I moved away from it in the first place.)	2025-02-07 13:58:09 +13:00
Akash Levy	66186f11fd	Merge branch 'YosysHQ:main' into main	2025-01-30 14:00:19 -08:00
Robin Ole Heinemann	0ab13924a5	write_verilog: log_abort on unhandled $check flavor	2025-01-30 14:18:02 +00:00
Robin Ole Heinemann	2f11dc87c9	write_verilog: emit $check cell names as labels	2025-01-30 14:18:02 +00:00
Akash Levy	f403256a34	Merge branch 'YosysHQ:main' into main	2025-01-23 14:06:16 -08:00
Catherine	3076803c9e	write_json: missing \n in help text.	2025-01-23 05:17:52 +00:00
Akash Levy	5c514e00a4	Sync with upstream	2025-01-13 17:20:59 -08:00
N. Engelhardt	77b28442a5	emit $scopeinfo cells by default	2025-01-08 14:47:46 +01:00
N. Engelhardt	dab7905cbe	write_json: add option to include $scopeinfo cells	2025-01-08 13:33:56 +01:00
Krystine Sherwin	7698dfba5e	smtr: Fix help text ... Can't take both [selection] and [filename] optional arguments.	2025-01-06 14:31:50 +13:00
Akash Levy	33b3d933de	Merge branch 'YosysHQ:main' into main	2024-12-25 04:25:25 -08:00
Catherine	1ef4c7f565	yosys-smtbmc: add cvc5 to help text.	2024-12-25 04:59:02 +00:00
Akash Levy	1dcf75d175	Sync	2024-12-19 21:40:30 -08:00
Emil J. Tywoniak	d071489ab1	hashlib: redo interface for flexibility	2024-12-18 14:49:25 +01:00
Akash Levy	caaef5ac14	Merge branch 'YosysHQ:main' into main	2024-12-11 12:00:34 -08:00
Martin Povišer	86fad8f6f5	Merge pull request #4803 from povik/write_verilog-buf ... write_verilog: Use assign for `$buf`	2024-12-10 20:10:58 +01:00
Martin Povišer	559209c856	abc_new: Fix PI confusion in whitebox model export	2024-12-10 14:27:29 +01:00
Martin Povišer	495a7805ec	aiger2: Support $extern: hierarchy ... `$extern:...` modules inserted by `techmap -extern` are special in the regard that they have a private ID (starting with a dollar sign) but are not an internal cell. Support those modules in xaiger export.	2024-12-10 14:27:29 +01:00
Martin Povišer	e7b21d2706	write_verilog: Use assign for $buf	2024-12-05 18:28:23 +01:00
Akash Levy	4356eae4c9	Yosys sync	2024-12-04 14:16:55 -08:00
Krystine Sherwin	e634e9c26b	aiger2: Resolve warnings ... - Remove unused statics CONST_FALSE and CONST_TRUE (which appear to have been folded into the `Index` declaration as CFALSE and CTRUE). - Assign default value of EMPTY_LIT to `a` and `b` for comparison ops. - Tag debug only variables with YS_MAYBE_UNUSED, don't assign unused variables (but continue to call the function because it moves the file pointer).	2024-12-03 14:01:57 +13:00
Krystine Sherwin	1de5d98ae2	Reduce comparisons of size_t and int ... `Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`. For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.	2024-11-29 12:53:29 +13:00
Akash Levy	1a69c51c88	Merge branch 'YosysHQ:main' into main	2024-11-18 16:10:30 -08:00
KrystalDelusion	dcff8b0666	Merge pull request #4719 from AdamLee7/main ... add select option for write_json	2024-11-19 08:42:38 +13:00
Akash Levy	5210d8614c	Merge	2024-11-17 22:46:05 -08:00
Akash Levy	ace558e90c	Simplify using module->ports, which is apparently sorted	2024-11-17 11:36:30 -08:00
Akash Levy	3a32729373	Remove keep_running variable (unused)	2024-11-17 10:40:04 -08:00
Akash Levy	8f9a0b680a	Fix O(N^2) port dump down to O(N)	2024-11-16 22:56:41 -08:00
Alain Dargelas	88c847f733	Oopsy!	2024-11-16 17:04:07 -08:00
Alain Dargelas	f011b74f87	Fix port dump n^2 -> n	2024-11-16 10:43:25 -08:00
Akash Levy	6be73e5c2e	Updates	2024-11-15 19:02:06 -08:00
Robin Ole Heinemann	6d4f056a35	cxxrtl: use debug attrs of alias not aliasee	2024-11-12 13:07:33 +00:00
Akash Levy	ea76abdaee	Merge	2024-11-11 11:47:58 -08:00
Robin Ole Heinemann	8bc4bd8a20	cxxrtl, fmt: escape double quotes in c strings	2024-11-11 18:49:05 +00:00
Jannis Harder	558b2f9ae9	Merge pull request #3953 from georgerennie/bug_3769 ... write_smt2: Check for constant bool after fully resolving signal	2024-11-11 16:23:35 +01:00
Jannis Harder	014cb531aa	Merge pull request #4645 from georgerennie/george/btor_undef_array_init ... write_btor: only initialize array with const value when it is fully def	2024-11-11 16:18:57 +01:00
Jannis Harder	261b44718d	Merge pull request #4641 from georgerennie/george/btor_undriven_wires ... write_btor: don't emit undriven bits multiple times	2024-11-11 16:17:25 +01:00
Akash Levy	fa50434708	Merge branch 'YosysHQ:main' into main	2024-11-08 14:10:24 -08:00
AdamLee7	7ed359fa7b	add select option for write_json	2024-11-07 17:48:06 +08:00
Krystine Sherwin	ee73a91f44	Remove references to ilang	2024-11-05 12:36:31 +13:00
Akash Levy	d63c793e72	Merge branch 'YosysHQ:main' into main	2024-10-28 11:24:55 -07:00
Martin Povišer	598f6c9de9	aiger2: Fix open-coded constants	2024-10-26 08:54:01 +02:00
Akash Levy	97a804ac12	Split large constants onto new lines in verilog backend	2024-10-25 15:52:19 -07:00
Akash Levy	1953a42f0d	Add new lines	2024-10-23 23:52:55 -07:00
Emil J. Tywoniak	785bd44da7	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00