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Merge branch 'YosysHQ:main' into main

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This commit is contained in:
Akash Levy 2024-11-08 14:10:24 -08:00 • committed by GitHub
commit fa50434708
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31 changed files with 49 additions and 71 deletions
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4
backends/btor/test_cells.sh
View file

@ -10,11 +10,11 @@ cd test_cells.tmp
for fn in test_*.il; do
../../../yosys -p "
read_ilang $fn
read_rtlil $fn
rename gold gate
synth
read_ilang $fn
read_rtlil $fn
miter -equiv -make_assert -flatten gold gate main
hierarchy -top main
write_btor ${fn%.il}.btor

15
backends/rtlil/rtlil_backend.cc
View file

@ -464,21 +464,6 @@ struct RTLILBackend : public Backend {
}
} RTLILBackend;
struct IlangBackend : public Backend {
IlangBackend() : Backend("ilang", "(deprecated) alias of write_rtlil") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log("See `help write_rtlil`.\n");
log("\n");
}
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
RTLILBackend.execute(f, filename, args, design);
}
} IlangBackend;
struct DumpPass : public Pass {
DumpPass() : Pass("dump", "print parts of the design in RTLIL format") { }
void help() override

2
backends/smt2/test_cells.sh
View file

@ -21,7 +21,7 @@ EOT
for x in $(set +x; ls test_*.il | sort -R); do
x=${x%.il}
cat > $x.ys <<- EOT
read_ilang $x.il
read_rtlil $x.il
copy gold gate
cd gate

4
backends/smv/test_cells.sh
View file

@ -17,11 +17,11 @@ EOT
for fn in test_*.il; do
../../../yosys -p "
read_ilang $fn
read_rtlil $fn
rename gold gate
synth
read_ilang $fn
read_rtlil $fn
miter -equiv -flatten gold gate main
hierarchy -top main
write_smv -tpl template.txt ${fn#.il}.smv