mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-25 01:55:33 +00:00
write_verilog -srcattronly option
This commit is contained in:
parent
e35032f2f6
commit
1b1882fe56
1 changed files with 1 additions and 1 deletions
|
@ -2420,7 +2420,7 @@ struct VerilogBackend : public Backend {
|
|||
log("\n");
|
||||
log(" -noattr\n");
|
||||
log(" with this option no attributes are included in the output\n");
|
||||
log(" -onlysrcattr\n");
|
||||
log(" -srcattronly\n");
|
||||
log(" with this option only src attributes are included in the output\n");
|
||||
log("\n");
|
||||
log(" -attr2comment\n");
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue