mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity

Fix port dump n^2 -> n

Browse source
This commit is contained in:
Alain Dargelas 2024-11-16 10:43:25 -08:00
parent 6be73e5c2e
commit f011b74f87
1 changed files with 22 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

35
backends/verilog/verilog_backend.cc
View file

@ -2347,20 +2347,29 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
}
dump_attributes(f, indent, module->attributes, "\n", /*modattr=*/true);
f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str());
bool keep_running = true;
f << stringf("%s"
"module %s(",
indent.c_str(), id(module->name, false).c_str());
int cnt = 0;
for (int port_id = 1; keep_running; port_id++) {
keep_running = false;
for (auto wire : module->wires()) {
if (wire->port_id == port_id) {
if (port_id != 1)
f << stringf(", ");
f << stringf("%s", id(wire->name).c_str());
keep_running = true;
if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++;
continue;
}
int max_port_id = 0;
for (auto wire : module->wires()) {
max_port_id = std::max(wire->port_id, max_port_id);
}
std::vector<Wire *> wires(max_port_id + 1, nullptr);
for (auto wire : module->wires()) {
wires[wire->port_id] = wire;
}
for (int port_id = 1; port_id < max_port_id; port_id++) {
Wire *wire = wires[port_id];
if (wire) {
if (port_id != 1)
f << stringf(", ");
f << stringf("%s", id(wire->name).c_str());
if (cnt == 20) {
f << stringf("\n");
cnt = 0;
} else
cnt++;
}
}
f << stringf(");\n");