mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-26 18:45:34 +00:00
Code Activity

write_verilog -srcattronly option

Browse source
This commit is contained in:
Alain Dargelas 2025-03-10 10:15:24 -07:00
parent 1b1882fe56
commit 268459e00a
1 changed files with 1 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
backends/verilog/verilog_backend.cc
View file

@ -2420,6 +2420,7 @@ struct VerilogBackend : public Backend {
log("\n");
log(" -noattr\n");
log(" with this option no attributes are included in the output\n");
log("\n");
log(" -srcattronly\n");
log(" with this option only src attributes are included in the output\n");
log("\n");