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write_verilog: emit $check cell names as labels
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@ -1044,16 +1044,21 @@ void dump_cell_expr_print(std::ostream &f, std::string indent, const RTLIL::Cell
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void dump_cell_expr_check(std::ostream &f, std::string indent, const RTLIL::Cell *cell)
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{
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std::string flavor = cell->getParam(ID(FLAVOR)).decode_string();
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std::string label = "";
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if (cell->name.isPublic()) {
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label = stringf("%s: ", id(cell->name).c_str());
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}
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if (flavor == "assert")
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f << stringf("%s" "assert (", indent.c_str());
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f << stringf("%s" "%s" "assert (", indent.c_str(), label.c_str());
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else if (flavor == "assume")
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f << stringf("%s" "assume (", indent.c_str());
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f << stringf("%s" "%s" "assume (", indent.c_str(), label.c_str());
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else if (flavor == "live")
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f << stringf("%s" "assert (eventually ", indent.c_str());
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f << stringf("%s" "%s" "assert (eventually ", indent.c_str(), label.c_str());
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else if (flavor == "fair")
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f << stringf("%s" "assume (eventually ", indent.c_str());
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f << stringf("%s" "%s" "assume (eventually ", indent.c_str(), label.c_str());
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else if (flavor == "cover")
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f << stringf("%s" "cover (", indent.c_str());
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f << stringf("%s" "%s" "cover (", indent.c_str(), label.c_str());
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dump_sigspec(f, cell->getPort(ID::A));
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f << stringf(");\n");
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}
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