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Split large constants onto new lines in verilog backend

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This commit is contained in:
Akash Levy 2024-10-25 15:52:19 -07:00
parent b65ddf9aa5
commit 97a804ac12
1 changed files with 13 additions and 0 deletions
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13
backends/verilog/verilog_backend.cc
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@ -363,6 +363,19 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
f << "{0{1'b0}}";
return;
}
if (sig.is_fully_const() && GetSize(sig) > 8192) {
f << stringf("{ ");
int i = 0;
for (auto it = sig.bits().rbegin(); it != sig.bits().rend(); ++it) {
dump_const(f, it->data, 1, 0);
if (it != sig.bits().rend() - 1)
f << stringf(", ");
if (i++ % 20 == 19)
f << stringf("\n");
}
f << stringf(" }");
return;
}
if (sig.is_chunk()) {
dump_sigchunk(f, sig.as_chunk());
} else {