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Merge pull request #4803 from povik/write_verilog-buf

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write_verilog: Use assign for `$buf`
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Martin Povišer 2024-12-10 20:10:58 +01:00 • committed by GitHub
commit 86fad8f6f5
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backends/verilog/verilog_backend.cc
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@ -1071,7 +1071,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == ID($_BUF_)) {
if (cell->type.in(ID($_BUF_), ID($buf))) {
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");