mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-30 07:53:16 +00:00
Code Activity

Merge branch 'YosysHQ:main' into main

Browse source
This commit is contained in:
Akash Levy 2024-12-11 12:00:34 -08:00 • committed by GitHub
commit caaef5ac14
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
21 changed files with 432 additions and 137 deletions
Download patch file Download diff file Expand all files Collapse all files

12
backends/aiger2/aiger.cc
View file

@ -832,12 +832,8 @@ struct XAigerAnalysis : Index<XAigerAnalysis, int, 0, 0> {
return false;
Cell *driver = bit.wire->driverCell();
if (!driver->type.isPublic())
return false;
Module *mod = design->module(driver->type);
log_assert(mod);
if (!mod->has_attribute(ID::abc9_box_id))
if (!mod || !mod->has_attribute(ID::abc9_box_id))
return false;
int max = 1;
@ -870,7 +866,7 @@ struct XAigerAnalysis : Index<XAigerAnalysis, int, 0, 0> {
HierCursor cursor;
for (auto box : top_minfo->found_blackboxes) {
Module *def = design->module(box->type);
if (!box->type.isPublic() || (def && !def->has_attribute(ID::abc9_box_id)))
if (!(def && def->has_attribute(ID::abc9_box_id)))
for (auto &conn : box->connections_)
if (box->output(conn.first))
for (auto bit : conn.second)
@ -885,7 +881,7 @@ struct XAigerAnalysis : Index<XAigerAnalysis, int, 0, 0> {
for (auto box : top_minfo->found_blackboxes) {
Module *def = design->module(box->type);
if (!box->type.isPublic() || (def && !def->has_attribute(ID::abc9_box_id)))
if (!(def && def->has_attribute(ID::abc9_box_id)))
for (auto &conn : box->connections_)
if (box->input(conn.first))
for (auto bit : conn.second)
@ -1106,7 +1102,7 @@ struct XAigerWriter : AigerWriter {
holes_module->ports.push_back(w->name);
holes_pis.push_back(w);
}
in_conn.append(holes_pis[i]);
in_conn.append(holes_pis[holes_pi_idx]);
holes_pi_idx++;
}
holes_wb->setPort(port_id, in_conn);

2
backends/verilog/verilog_backend.cc
View file

@ -1087,7 +1087,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == ID($_BUF_)) {
if (cell->type.in(ID($_BUF_), ID($buf))) {
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");