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This commit is contained in:
Akash Levy 2024-10-23 23:52:55 -07:00
parent 17c8567b02
commit 1953a42f0d
1 changed files with 3 additions and 0 deletions
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3
backends/verilog/verilog_backend.cc
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@ -367,9 +367,12 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
dump_sigchunk(f, sig.as_chunk());
} else {
f << stringf("{ ");
int i = 0;
for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); ++it) {
if (it != sig.chunks().rbegin())
f << stringf(", ");
if (i++ % 20 == 19)
f << stringf("\n");
dump_sigchunk(f, *it, true);
}
f << stringf(" }");