1166 commits

Author	SHA1	Message	Date
Eddie Hung	08139aa53a	xilinx_srl now copes with word-level flops $dff{,e}	2019-08-23 12:22:46 -07:00
Eddie Hung	78b7d8f531	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	2019-08-23 11:32:44 -07:00
Eddie Hung	509c353fe9	Forgot one	2019-08-23 11:23:50 -07:00
Eddie Hung	a270af00cc	Put abc_* attributes above port	2019-08-23 11:21:44 -07:00
Eddie Hung	7188972645	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	2019-08-22 10:32:54 -07:00
Clifford Wolf	151db528e4	Fix missing newline at end of file ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-22 18:09:37 +02:00
Clifford Wolf	2c8c8b3c74	Merge pull request #1289 from mmicko/anlogic_fixes ... Anlogic fixes and optimization	2019-08-22 18:09:10 +02:00
Clifford Wolf	4c449caf9b	Fix missing newline at end of file ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-22 18:06:36 +02:00
Clifford Wolf	4d37710e82	Merge pull request #1281 from mmicko/efinix ... Initial support for Efinix Trion series FPGAs	2019-08-22 18:06:02 +02:00
Eddie Hung	15188033da	Add variable length support to xilinx_srl	2019-08-21 17:34:40 -07:00
Eddie Hung	edec73fec1	abc9 to perform new 'map_ffs' before 'map_luts'	2019-08-21 15:37:55 -07:00
Eddie Hung	5ce0c31d0e	Add init support	2019-08-21 13:05:10 -07:00
Eddie Hung	076af2e617	Missing newline	2019-08-20 20:37:52 -07:00
Eddie Hung	33960dd3d8	Merge pull request #1209 from YosysHQ/eddie/synth_xilinx ... [WIP] synth xilinx renaming, as per #1184	2019-08-20 12:55:26 -07:00
Eddie Hung	14c03861b6	Merge pull request #1304 from YosysHQ/eddie/abc9_refactor ... Refactor abc9 to use port attributes, not module attributes	2019-08-20 11:59:31 -07:00
Eddie Hung	d9fe4cccbf	Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx	2019-08-20 11:57:52 -07:00
Eddie Hung	d81a090d89	Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro	2019-08-19 09:56:17 -07:00
Miodrag Milanovic	4a32e29445	Merge remote-tracking branch 'upstream/master' into anlogic_fixes	2019-08-18 11:47:46 +02:00
whitequark	101235400c	Merge branch 'master' into eddie/pr1266_again	2019-08-18 08:04:10 +00:00
Eddie Hung	1c57b1e7ea	Update abc_* attr in ecp5 and ice40	2019-08-16 15:56:57 -07:00
Eddie Hung	562c9e3624	Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules	2019-08-16 15:40:53 -07:00
Eddie Hung	41191f1ea4	Merge pull request #1250 from bwidawsk/master ... techlibs/intel: Clean up Makefile	2019-08-16 14:07:09 -07:00
Eddie Hung	8a2480526f	Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER	2019-08-12 12:19:25 -07:00
Eddie Hung	12c692f6ed	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" ... This reverts commit c851dc1310, reversing changes made to f54bf1631f.	2019-08-12 12:06:45 -07:00
Miodrag Milanovic	5f561bdcb1	Proper arith for Anlogic and use standard pass	2019-08-12 20:21:36 +02:00
Miodrag Milanovic	2897fe4d09	Fix formating	2019-08-11 17:05:24 +02:00
Miodrag Milanovic	ead2b52b5a	one bit enable signal	2019-08-11 13:59:39 +02:00
Miodrag Milanovic	aa0c37722a	fix mixing signals on FF mapping	2019-08-11 11:40:15 +02:00
Miodrag Milanovic	853c755a0c	Replaced custom step with setundef	2019-08-11 11:01:46 +02:00
Miodrag Milanovic	e609537e38	Fixed data width	2019-08-11 10:46:48 +02:00
Miodrag Milanovic	8c8100e0df	Adding new pass to fix carry chain	2019-08-11 10:17:49 +02:00
Miodrag Milanovic	b3a91d6508	cleanup	2019-08-11 08:37:56 +02:00
David Shah	f9020ce2b3	Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"	2019-08-10 17:14:48 +01:00
Clifford Wolf	f54bf1631f	Merge pull request #1258 from YosysHQ/eddie/cleanup ... Cleanup a few barnacles across codebase	2019-08-10 09:52:14 +02:00
Clifford Wolf	a469d1a64a	Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc ... Add a few comments to document $alu and $lcu	2019-08-10 09:46:46 +02:00
Eddie Hung	041defc5a6	Reformat so it shows up/looks nice when "help $alu" and "help $alu+"	2019-08-09 12:33:39 -07:00
Eddie Hung	acfb672d34	A bit more on where $lcu comes from	2019-08-09 09:50:47 -07:00
Eddie Hung	5aef998957	Add more comments	2019-08-09 09:48:17 -07:00
Miodrag Milanovic	d51b135e33	Fix CO	2019-08-09 12:37:10 +02:00
Miodrag Milanovic	7a860c5623	Merge remote-tracking branch 'upstream/master' into efinix	2019-08-09 09:46:37 +02:00
Eddie Hung	dae7c59358	Add a few comments to document $alu and $lcu	2019-08-08 10:05:28 -07:00
Eddie Hung	9776084eda	Allow whitebox modules to be overwritten	2019-08-07 16:40:24 -07:00
Eddie Hung	675c1d4218	Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER	2019-08-07 16:29:38 -07:00
Eddie Hung	cc331cf70d	Add test	2019-08-07 16:29:38 -07:00
Eddie Hung	ea8ac8fd74	Remove ice40_unlut	2019-08-07 16:29:38 -07:00
Eddie Hung	6b314c8371	Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER	2019-08-07 16:29:38 -07:00
Eddie Hung	6d77236f38	substr() -> compare()	2019-08-07 12:20:08 -07:00
Eddie Hung	7164996921	RTLIL::S{0,1} -> State::S{0,1}	2019-08-07 11:12:38 -07:00
Eddie Hung	e6d5147214	Merge remote-tracking branch 'origin/master' into eddie/cleanup	2019-08-07 11:11:50 -07:00
Eddie Hung	48d0f99406	stoi -> atoi	2019-08-07 11:09:17 -07:00