mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 02:45:52 +00:00
Code Activity

Fix missing newline at end of file

Browse source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-08-22 18:09:37 +02:00
parent 2c8c8b3c74
commit 151db528e4
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/anlogic/arith_map.v
View file

@ -81,4 +81,4 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
/* End implementation */
assign X = AA ^ BB;
endmodule
endmodule