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Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
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David Shah
GitHub
parent
f54bf1631f
commit
f9020ce2b3
20 changed files with 181 additions and 181 deletions
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@ -4,6 +4,7 @@ OBJS += techlibs/ice40/ice40_braminit.o
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OBJS += techlibs/ice40/ice40_ffssr.o
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OBJS += techlibs/ice40/ice40_ffinit.o
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OBJS += techlibs/ice40/ice40_opt.o
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OBJS += techlibs/ice40/ice40_unlut.o
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GENFILES += techlibs/ice40/brams_init1.vh
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GENFILES += techlibs/ice40/brams_init2.vh
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@ -44,21 +44,35 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
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genvar i;
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
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\$__ICE40_CARRY_WRAPPER #(
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// A[0]: 1010 1010 1010 1010
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// A[1]: 1100 1100 1100 1100
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// A[2]: 1111 0000 1111 0000
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// A[3]: 1111 1111 0000 0000
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.LUT(16'b 0110_1001_1001_0110)
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) fadd (
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`ifdef _ABC
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\$__ICE40_FULL_ADDER carry (
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.A(AA[i]),
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.B(BB[i]),
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.CI(C[i]),
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.I0(1'b0),
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.I3(C[i]),
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.CO(CO[i]),
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.O(Y[i])
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);
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`else
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SB_CARRY carry (
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.I0(AA[i]),
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.I1(BB[i]),
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.CI(C[i]),
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.CO(CO[i])
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);
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SB_LUT4 #(
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// I0: 1010 1010 1010 1010
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// I1: 1100 1100 1100 1100
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// I2: 1111 0000 1111 0000
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// I3: 1111 1111 0000 0000
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.LUT_INIT(16'b 0110_1001_1001_0110)
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) adder (
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.I0(1'b0),
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.I1(AA[i]),
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.I2(BB[i]),
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.I3(C[i]),
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.O(Y[i])
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);
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`endif
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end endgenerate
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assign X = AA ^ BB;
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@ -62,21 +62,26 @@ module \$lut (A, Y);
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endmodule
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`endif
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`ifndef NO_ADDER
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module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
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parameter LUT = 0;
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`ifdef _ABC
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module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
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SB_CARRY carry (
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.I0(A),
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.I1(B),
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.CI(CI),
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.CO(CO)
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);
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\$lut #(
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.WIDTH(4),
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.LUT(LUT)
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) lut (
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.A({I3,B,A,I0}),
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.Y(O)
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SB_LUT4 #(
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// I0: 1010 1010 1010 1010
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// I1: 1100 1100 1100 1100
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// I2: 1111 0000 1111 0000
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// I3: 1111 1111 0000 0000
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.LUT_INIT(16'b 0110_1001_1001_0110)
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) adder (
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.I0(1'b0),
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.I1(A),
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.I2(B),
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.I3(CI),
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.O(O)
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);
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endmodule
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`endif
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106
techlibs/ice40/ice40_unlut.cc
Normal file
106
techlibs/ice40/ice40_unlut.cc
Normal file
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@ -0,0 +1,106 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include <stdlib.h>
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#include <stdio.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static SigBit get_bit_or_zero(const SigSpec &sig)
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{
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if (GetSize(sig) == 0)
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return State::S0;
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return sig[0];
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}
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static void run_ice40_unlut(Module *module)
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{
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SigMap sigmap(module);
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\SB_LUT4")
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{
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SigSpec inbits;
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inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
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inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
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inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
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inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
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sigmap.apply(inbits);
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log("Mapping SB_LUT4 cell %s.%s to $lut.\n", log_id(module), log_id(cell));
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cell->type ="$lut";
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cell->setParam("\\WIDTH", 4);
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cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
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cell->unsetParam("\\LUT_INIT");
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cell->setPort("\\A", SigSpec({
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get_bit_or_zero(cell->getPort("\\I0")),
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get_bit_or_zero(cell->getPort("\\I1")),
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get_bit_or_zero(cell->getPort("\\I2")),
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get_bit_or_zero(cell->getPort("\\I3"))
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}));
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cell->setPort("\\Y", cell->getPort("\\O")[0]);
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cell->unsetPort("\\I0");
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cell->unsetPort("\\I1");
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cell->unsetPort("\\I2");
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cell->unsetPort("\\I3");
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cell->unsetPort("\\O");
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cell->check();
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}
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}
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}
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struct Ice40UnlutPass : public Pass {
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Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SB_LUT4 cells to $lut cells") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" ice40_unlut [options] [selection]\n");
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log("\n");
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log("This command transforms all SB_LUT4 cells to generic $lut cells.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing ICE40_UNLUT pass (convert SB_LUT4 to $lut).\n");
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log_push();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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// if (args[argidx] == "-???") {
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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run_ice40_unlut(module);
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}
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} Ice40UnlutPass;
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PRIVATE_NAMESPACE_END
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@ -238,7 +238,7 @@ struct SynthIce40Pass : public ScriptPass
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{
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if (check_label("begin"))
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{
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run("read_verilog -icells -lib +/ice40/cells_sim.v");
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run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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run("proc");
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}
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@ -293,10 +293,8 @@ struct SynthIce40Pass : public ScriptPass
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{
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if (nocarry)
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run("techmap");
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else {
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run("ice40_wrapcarry");
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run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
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}
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else
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run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : ""));
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if (retime || help_mode)
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run(abc + " -dff", "(only if -retime)");
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run("ice40_opt");
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@ -311,7 +309,7 @@ struct SynthIce40Pass : public ScriptPass
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run("opt_merge");
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run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
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}
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run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
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run("techmap -D NO_LUT -map +/ice40/cells_map.v");
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run("opt_expr -mux_undef");
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run("simplemap");
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run("ice40_ffinit");
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@ -340,12 +338,13 @@ struct SynthIce40Pass : public ScriptPass
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else
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wire_delay = 250;
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run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
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run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v");
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}
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else
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run(abc + " -dress -lut 4", "(skip if -noabc)");
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}
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run("techmap -D NO_LUT -map +/ice40/cells_map.v");
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run("clean");
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run("ice40_unlut");
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run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
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}
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@ -1,5 +1,6 @@
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read_verilog test_arith.v
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synth_ice40
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techmap -map ../cells_sim.v
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rename test gate
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read_verilog test_arith.v
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@ -7,11 +8,3 @@ rename test gold
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miter -equiv -flatten -make_outputs gold gate miter
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sat -verify -prove trigger 0 -show-ports miter
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synth_ice40 -top gate
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read_verilog test_arith.v
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rename test gold
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miter -equiv -flatten -make_outputs gold gate miter
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sat -verify -prove trigger 0 -show-ports miter
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