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Merge pull request #1258 from YosysHQ/eddie/cleanup

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Cleanup a few barnacles across codebase
This commit is contained in:
Clifford Wolf 2019-08-10 09:52:14 +02:00 • committed by GitHub
commit f54bf1631f
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GPG key ID: 4AEE18F83AFDEB23
69 changed files with 405 additions and 414 deletions
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22
techlibs/coolrunner2/coolrunner2_sop.cc
View file

@ -60,10 +60,8 @@ struct Coolrunner2SopPass : public Pass {
dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_inv;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE" ||
cell->type == "\\LDCP" || cell->type == "\\LDCP_N")
if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\FTCP", "\\FTCP_N", "\\FTDCP",
"\\FDCPE", "\\FDCPE_N", "\\FDDCPE", "\\LDCP", "\\LDCP_N"))
{
if (cell->hasPort("\\PRE"))
special_pterms_no_inv[sigmap(cell->getPort("\\PRE")[0])].insert(
@ -257,10 +255,8 @@ struct Coolrunner2SopPass : public Pass {
pool<SigBit> sig_fed_by_ff;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
cell->type == "\\LDCP" || cell->type == "\\LDCP_N" ||
cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE")
if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
{
auto output = sigmap(cell->getPort("\\Q")[0]);
sig_fed_by_ff.insert(output);
@ -270,13 +266,11 @@ struct Coolrunner2SopPass : public Pass {
// Look at all the FF inputs
for (auto cell : module->selected_cells())
{
if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
cell->type == "\\LDCP" || cell->type == "\\LDCP_N" ||
cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE")
if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
{
SigBit input;
if (cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP")
if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
input = sigmap(cell->getPort("\\T")[0]);
else
input = sigmap(cell->getPort("\\D")[0]);
@ -300,7 +294,7 @@ struct Coolrunner2SopPass : public Pass {
xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
xor_cell->setPort("\\OUT", xor_to_ff_wire);
if (cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP")
if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
cell->setPort("\\T", xor_to_ff_wire);
else
cell->setPort("\\D", xor_to_ff_wire);

6
techlibs/ice40/ice40_braminit.cc
View file

@ -69,13 +69,13 @@ static void run_ice40_braminit(Module *module)
for (int i = 0; i < GetSize(line); i++)
{
if (in_comment && line.substr(i, 2) == "*/") {
if (in_comment && line.compare(i, 2, "*/") == 0) {
line[i] = ' ';
line[i+1] = ' ';
in_comment = false;
continue;
}
if (!in_comment && line.substr(i, 2) == "/*")
if (!in_comment && line.compare(i, 2, "/*") == 0)
in_comment = true;
if (in_comment)
line[i] = ' ';
@ -87,7 +87,7 @@ static void run_ice40_braminit(Module *module)
long value;
token = next_token(line, " \t\r\n");
if (token.empty() || token.substr(0, 2) == "//")
if (token.empty() || token.compare(0, 2, "//") == 0)
break;
if (token[0] == '@') {

2
techlibs/ice40/ice40_opt.cc
View file

@ -117,7 +117,7 @@ static void run_ice40_opts(Module *module)
log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut";
cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] });
cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
cell->setPort("\\Y", cell->getPort("\\O"));
cell->unsetPort("\\B");
cell->unsetPort("\\CI");

2
techlibs/ice40/synth_ice40.cc
View file

@ -183,7 +183,7 @@ struct SynthIce40Pass : public ScriptPass
continue;
}
if (args[argidx] == "-dffe_min_ce_use" && argidx+1 < args.size()) {
min_ce_use = std::stoi(args[++argidx]);
min_ce_use = atoi(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-nobram") {

2
techlibs/xilinx/synth_xilinx.cc
View file

@ -195,7 +195,7 @@ struct SynthXilinxPass : public ScriptPass
continue;
}
if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
widemux = std::stoi(args[++argidx]);
widemux = atoi(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-abc9") {