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Add a few comments to document $alu and $lcu

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Eddie Hung 2019-08-08 10:05:28 -07:00
parent 3414ee1e3f
commit dae7c59358
1 changed files with 12 additions and 9 deletions
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21
techlibs/common/simlib.v
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@ -532,14 +532,15 @@ endmodule
// --------------------------------------------------------
module \$lcu (P, G, CI, CO);
module \$lcu (P, G, CI, CO); // Lookahead carry unit
parameter WIDTH = 1;
input [WIDTH-1:0] P, G;
input CI;
input [WIDTH-1:0] P; // Propagate
input [WIDTH-1:0] G; // Generate
input CI; // Carry-in
output reg [WIDTH-1:0] CO;
output reg [WIDTH-1:0] CO; // Carry-out
integer i;
always @* begin
@ -563,12 +564,14 @@ parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input [A_WIDTH-1:0] A; // Input operand
input [B_WIDTH-1:0] B; // Input operand
output [Y_WIDTH-1:0] X; // A xor B (sign-extended, optional B inversion)
output [Y_WIDTH-1:0] Y; // Sum
input CI, BI;
output [Y_WIDTH-1:0] CO;
input CI; // Carry-in
input BI; // Invert-B
output [Y_WIDTH-1:0] CO; // Carry-out
wire [Y_WIDTH-1:0] AA, BB;