mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00
Code Activity

Allow whitebox modules to be overwritten

Browse source
This commit is contained in:
Eddie Hung 2019-08-07 16:40:24 -07:00
parent 9962e6fc1a
commit 9776084eda
2 changed files with 1 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/ice40/tests/test_arith.ys
View file

@ -8,8 +8,6 @@ rename test gold
miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter
delete A:whitebox # Necessary since whiteboxes cannot
# be overwritten...
synth_ice40 -top gate
read_verilog test_arith.v