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one bit enable signal
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module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 8;
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parameter CFG_DBITS = 20;
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parameter CFG_ENABLE_A = 2;
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parameter CFG_ENABLE_A = 1;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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