mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 11:25:53 +00:00
Code Activity

one bit enable signal

Browse source
This commit is contained in:
Miodrag Milanovic 2019-08-11 13:59:39 +02:00
parent aa0c37722a
commit ead2b52b5a
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/efinix/brams_map.v
View file

@ -1,7 +1,7 @@
module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 8;
parameter CFG_DBITS = 20;
parameter CFG_ENABLE_A = 2;
parameter CFG_ENABLE_A = 1;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;