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Merge pull request #1304 from YosysHQ/eddie/abc9_refactor

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Refactor abc9 to use port attributes, not module attributes
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Eddie Hung 2019-08-20 11:59:31 -07:00 • committed by GitHub
commit 14c03861b6
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6 changed files with 138 additions and 104 deletions
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22
techlibs/ecp5/cells_sim.v
View file

@ -15,10 +15,13 @@ module L6MUX21 (input D0, D1, SD, output Z);
endmodule
// ---------------------------------------
(* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *)
module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
output S0, S1, COUT);
(* abc_box_id=1, lib_whitebox *)
module CCU2C(
(* abc_carry *) input CIN,
input A0, B0, C0, D0, A1, B1, C1, D1,
output S0, S1,
(* abc_carry *) output COUT
);
parameter [15:0] INIT0 = 16'h0000;
parameter [15:0] INIT1 = 16'h0000;
parameter INJECT1_0 = "YES";
@ -104,12 +107,13 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
endmodule
// ---------------------------------------
//(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *)
//(* abc_box_id=2 *)
module TRELLIS_DPR16X4 (
input [3:0] DI,
input [3:0] WAD,
input WRE, WCK,
input [3:0] RAD,
(* abc_scc_break *) input [3:0] DI,
(* abc_scc_break *) input [3:0] WAD,
(* abc_scc_break *) input WRE,
input WCK,
input [3:0] RAD,
output [3:0] DO
);
parameter WCKMUX = "WCK";

10
techlibs/ice40/cells_sim.v
View file

@ -141,8 +141,14 @@ module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule
(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
(* abc_box_id = 1, lib_whitebox *)
module \$__ICE40_FULL_ADDER (
(* abc_carry *) output CO,
output O,
input A,
input B,
(* abc_carry *) input CI
);
SB_CARRY carry (
.I0(A),
.I1(B),

28
techlibs/xilinx/cells_sim.v
View file

@ -181,8 +181,14 @@ module XORCY(output O, input CI, LI);
assign O = CI ^ LI;
endmodule
(* abc_box_id = 4, abc_carry="CI,CO", lib_whitebox *)
module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
(* abc_box_id = 4, lib_whitebox *)
module CARRY4(
(* abc_carry *) output [3:0] CO,
output [3:0] O,
(* abc_carry *) input CI,
input CYINIT,
input [3:0] DI, S
);
assign O = S ^ {CO[2:0], CI | CYINIT};
assign CO[0] = S[0] ? CI | CYINIT : DI[0];
assign CO[1] = S[1] ? CO[0] : DI[1];
@ -289,10 +295,12 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
(* abc_box_id = 5, abc_scc_break="D,WE" *)
(* abc_box_id = 5 *)
module RAM32X1D (
output DPO, SPO,
input D, WCLK, WE,
(* abc_scc_break *) input D,
input WCLK,
(* abc_scc_break *) input WE,
input A0, A1, A2, A3, A4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
@ -307,10 +315,12 @@ module RAM32X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
(* abc_box_id = 6, abc_scc_break="D,WE" *)
(* abc_box_id = 6 *)
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,
(* abc_scc_break *) input D,
input WCLK,
(* abc_scc_break *) input WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
@ -325,10 +335,12 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
(* abc_box_id = 7, abc_scc_break="D,WE" *)
(* abc_box_id = 7 *)
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,
(* abc_scc_break *) input D,
input WCLK,
(* abc_scc_break *) input WE,
input [6:0] A, DPRA
);
parameter INIT = 128'h0;