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Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro

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This commit is contained in:
Eddie Hung 2019-08-19 09:56:17 -07:00
parent 5abe133323
commit d81a090d89
4 changed files with 12 additions and 12 deletions
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4
techlibs/ecp5/cells_sim.v
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@ -17,10 +17,10 @@ endmodule
// ---------------------------------------
(* abc_box_id=1, lib_whitebox *)
module CCU2C(
(* abc_carry_in *) input CIN,
(* abc_carry *) input CIN,
input A0, B0, C0, D0, A1, B1, C1, D1,
output S0, S1,
(* abc_carry_out *) output COUT
(* abc_carry *) output COUT
);
parameter [15:0] INIT0 = 16'h0000;
parameter [15:0] INIT1 = 16'h0000;

4
techlibs/ice40/cells_sim.v
View file

@ -143,11 +143,11 @@ endmodule
(* abc_box_id = 1, lib_whitebox *)
module \$__ICE40_FULL_ADDER (
(* abc_carry_out *) output CO,
(* abc_carry *) output CO,
output O,
input A,
input B,
(* abc_carry_in *) input CI
(* abc_carry *) input CI
);
SB_CARRY carry (
.I0(A),

4
techlibs/xilinx/cells_sim.v
View file

@ -183,9 +183,9 @@ endmodule
(* abc_box_id = 4, lib_whitebox *)
module CARRY4(
(* abc_carry_out *) output [3:0] CO,
(* abc_carry *) output [3:0] CO,
output [3:0] O,
(* abc_carry_in *) input CI,
(* abc_carry *) input CI,
input CYINIT,
input [3:0] DI, S
);