mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 19:05:52 +00:00
Code Activity

Fix formating

Browse source
This commit is contained in:
Miodrag Milanovic 2019-08-11 17:05:24 +02:00
parent ead2b52b5a
commit 2897fe4d09
1 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
techlibs/efinix/arith_map.v
View file

@ -33,8 +33,8 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
input CI, BI;
output [Y_WIDTH-1:0] CO;
wire CIx;
wire [Y_WIDTH-1:0] COx;
wire CIx;
wire [Y_WIDTH-1:0] COx;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;