mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-24 01:25:33 +00:00
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
This commit is contained in:
Eddie Hung
commit
d9fe4cccbf
191 changed files with 6974 additions and 4473 deletions
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@ -50,7 +50,7 @@ struct AnlogicDetermineInitPass : public Pass {
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extra_args(args, args.size(), design);
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size_t cnt = 0;
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int cnt = 0;
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for (auto module : design->selected_modules())
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{
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for (auto cell : module->selected_cells())
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@ -65,7 +65,7 @@ struct AnlogicDetermineInitPass : public Pass {
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}
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}
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}
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log_header(design, "Updated %lu cells with determined init value.\n", cnt);
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log_header(design, "Updated %d cells with determined init value.\n", cnt);
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}
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} AnlogicDetermineInitPass;
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@ -69,7 +69,7 @@ struct AnlogicEqnPass : public Pass {
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extra_args(args, args.size(), design);
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size_t cnt = 0;
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int cnt = 0;
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for (auto module : design->selected_modules())
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{
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for (auto cell : module->selected_cells())
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@ -106,7 +106,7 @@ struct AnlogicEqnPass : public Pass {
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}
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}
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}
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log_header(design, "Updated %lu of AL_MAP_LUT* elements with equation.\n", cnt);
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log_header(design, "Updated %d of AL_MAP_LUT* elements with equation.\n", cnt);
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}
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} AnlogicEqnPass;
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@ -42,10 +42,9 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
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wire [Y_WIDTH-1:0] AA = A_buf;
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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wire [Y_WIDTH+1:0] COx;
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wire [Y_WIDTH+1:0] C = {COx, CI};
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wire [Y_WIDTH+2:0] C = {COx, CI};
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wire dummy;
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(* keep *)
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AL_MAP_ADDER #(
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.ALUTYPE("ADD_CARRY"))
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adder_cin (
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@ -55,19 +54,6 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
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genvar i;
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
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if(i==Y_WIDTH-1) begin
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(* keep *)
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AL_MAP_ADDER #(
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.ALUTYPE("ADD"))
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adder_cout (
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.c(C[Y_WIDTH]),
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.o(COx[Y_WIDTH])
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);
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assign CO = COx[Y_WIDTH];
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end
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else
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begin
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(* keep *)
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AL_MAP_ADDER #(
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.ALUTYPE("ADD")
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) adder_i (
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@ -76,9 +62,15 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
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.c(C[i+1]),
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.o({COx[i+1],Y[i]})
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);
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end
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end: slice
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endgenerate
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/* End implementation */
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AL_MAP_ADDER #(
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.ALUTYPE("ADD"))
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adder_cout (
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.c(C[Y_WIDTH+1]),
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.o(COx[Y_WIDTH+1])
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);
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assign CO = COx[Y_WIDTH+1];
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assign X = AA ^ BB;
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endmodule
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@ -228,6 +228,25 @@ output Y;
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assign Y = S ? B : A;
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endmodule
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_NMUX_ (A, B, S, Y)
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//-
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//- A 2-input inverting MUX gate.
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//-
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//- Truth table: A B S | Y
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//- -------+---
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//- 0 - 0 | 1
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//- 1 - 0 | 0
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//- - 0 1 | 1
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//- - 1 1 | 0
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//-
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module \$_NMUX_ (A, B, S, Y);
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input A, B, S;
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output Y;
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assign Y = S ? !B : !A;
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endmodule
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $_MUX4_ (A, B, C, D, S, T, Y)
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@ -532,14 +532,26 @@ endmodule
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// --------------------------------------------------------
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $lcu (P, G, CI, CO)
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//-
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//- Lookahead carry unit
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//- A building block dedicated to fast computation of carry-bits used in binary
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//- arithmetic operations. By replacing the ripple carry structure used in full-adder
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//- blocks, the more significant bits of the sum can be expected to be computed more
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//- quickly.
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//- Typically created during `techmap` of $alu cells (see the "_90_alu" rule in
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//- +/techmap.v).
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module \$lcu (P, G, CI, CO);
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parameter WIDTH = 1;
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input [WIDTH-1:0] P, G;
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input CI;
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input [WIDTH-1:0] P; // Propagate
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input [WIDTH-1:0] G; // Generate
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input CI; // Carry-in
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output reg [WIDTH-1:0] CO;
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output reg [WIDTH-1:0] CO; // Carry-out
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integer i;
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always @* begin
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@ -555,6 +567,17 @@ endmodule
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// --------------------------------------------------------
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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//-
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//- $alu (A, B, CI, BI, X, Y, CO)
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//-
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//- Arithmetic logic unit.
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//- A building block supporting both binary addition/subtraction operations, and
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//- indirectly, comparison operations.
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//- Typically created by the `alumacc` pass, which transforms:
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//- $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex
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//- cells into this $alu cell.
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//-
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module \$alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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@ -563,12 +586,16 @@ parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] X, Y;
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input [A_WIDTH-1:0] A; // Input operand
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input [B_WIDTH-1:0] B; // Input operand
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output [Y_WIDTH-1:0] X; // A xor B (sign-extended, optional B inversion,
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// used in combination with
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// reduction-AND for $eq/$ne ops)
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output [Y_WIDTH-1:0] Y; // Sum
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input CI, BI;
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output [Y_WIDTH-1:0] CO;
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input CI; // Carry-in (set for $sub)
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input BI; // Invert-B (set for $sub)
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output [Y_WIDTH-1:0] CO; // Carry-out
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wire [Y_WIDTH-1:0] AA, BB;
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@ -584,6 +611,7 @@ endgenerate
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wire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};
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assign X = AA ^ BB;
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// Full adder
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assign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};
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function get_carry;
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@ -60,10 +60,8 @@ struct Coolrunner2SopPass : public Pass {
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dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_inv;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
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cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
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cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE" ||
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cell->type == "\\LDCP" || cell->type == "\\LDCP_N")
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if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\FTCP", "\\FTCP_N", "\\FTDCP",
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"\\FDCPE", "\\FDCPE_N", "\\FDDCPE", "\\LDCP", "\\LDCP_N"))
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{
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if (cell->hasPort("\\PRE"))
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special_pterms_no_inv[sigmap(cell->getPort("\\PRE")[0])].insert(
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@ -257,10 +255,8 @@ struct Coolrunner2SopPass : public Pass {
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pool<SigBit> sig_fed_by_ff;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
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cell->type == "\\LDCP" || cell->type == "\\LDCP_N" ||
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cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
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cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE")
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if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
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"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
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{
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auto output = sigmap(cell->getPort("\\Q")[0]);
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sig_fed_by_ff.insert(output);
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@ -270,13 +266,11 @@ struct Coolrunner2SopPass : public Pass {
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// Look at all the FF inputs
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" ||
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cell->type == "\\LDCP" || cell->type == "\\LDCP_N" ||
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cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
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cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE")
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if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
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"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
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{
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SigBit input;
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if (cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP")
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if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
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input = sigmap(cell->getPort("\\T")[0]);
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else
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input = sigmap(cell->getPort("\\D")[0]);
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@ -300,7 +294,7 @@ struct Coolrunner2SopPass : public Pass {
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xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
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xor_cell->setPort("\\OUT", xor_to_ff_wire);
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if (cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP")
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if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
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cell->setPort("\\T", xor_to_ff_wire);
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else
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cell->setPort("\\D", xor_to_ff_wire);
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@ -333,6 +333,31 @@ module TRELLIS_SLICE(
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parameter [127:0] CCU2_INJECT1_0 = "NO";
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parameter [127:0] CCU2_INJECT1_1 = "NO";
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parameter WREMUX = "WRE";
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parameter WCKMUX = "WCK";
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parameter A0MUX = "A0";
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parameter A1MUX = "A1";
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parameter B0MUX = "B0";
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parameter B1MUX = "B1";
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parameter C0MUX = "C0";
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parameter C1MUX = "C1";
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parameter D0MUX = "D0";
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parameter D1MUX = "D1";
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wire A0m, B0m, C0m, D0m;
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wire A1m, B1m, C1m, D1m;
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generate
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if (A0MUX == "1") assign A0m = 1'b1; else assign A0m = A0;
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if (B0MUX == "1") assign B0m = 1'b1; else assign B0m = B0;
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if (C0MUX == "1") assign C0m = 1'b1; else assign C0m = C0;
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if (D0MUX == "1") assign D0m = 1'b1; else assign D0m = D0;
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if (A1MUX == "1") assign A1m = 1'b1; else assign A1m = A1;
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if (B1MUX == "1") assign B1m = 1'b1; else assign B1m = B1;
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if (C1MUX == "1") assign C1m = 1'b1; else assign C1m = C1;
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if (D1MUX == "1") assign D1m = 1'b1; else assign D1m = D1;
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endgenerate
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function [15:0] permute_initval;
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input [15:0] initval;
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@ -350,13 +375,13 @@ module TRELLIS_SLICE(
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LUT4 #(
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.INIT(LUT0_INITVAL)
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) lut4_0 (
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.A(A0), .B(B0), .C(C0), .D(D0),
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.A(A0m), .B(B0m), .C(C0m), .D(D0m),
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.Z(F0)
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);
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LUT4 #(
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.INIT(LUT1_INITVAL)
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) lut4_1 (
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.A(A1), .B(B1), .C(C1), .D(D1),
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.A(A1m), .B(B1m), .C(C1m), .D(D1m),
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.Z(F1)
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);
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// LUT expansion muxes
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@ -370,20 +395,20 @@ module TRELLIS_SLICE(
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.INJECT1_1(CCU2_INJECT1_1)
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) ccu2c_i (
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.CIN(FCI),
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.A0(A0), .B0(B0), .C0(C0), .D0(D0),
|
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.A1(A1), .B1(B1), .C1(C1), .D1(D1),
|
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.A0(A0m), .B0(B0m), .C0(C0m), .D0(D0m),
|
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.A1(A1m), .B1(B1m), .C1(C1m), .D1(D1m),
|
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.S0(F0), .S1(F1),
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.COUT(FCO)
|
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);
|
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end else if (MODE == "RAMW") begin
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assign WDO0 = C1;
|
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assign WDO1 = A1;
|
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assign WDO2 = D1;
|
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assign WDO3 = B1;
|
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assign WADO0 = D0;
|
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assign WADO1 = B0;
|
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assign WADO2 = C0;
|
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assign WADO3 = A0;
|
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assign WDO0 = C1m;
|
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assign WDO1 = A1m;
|
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assign WDO2 = D1m;
|
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assign WDO3 = B1m;
|
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assign WADO0 = D0m;
|
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assign WADO1 = B0m;
|
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assign WADO2 = C0m;
|
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assign WADO3 = A0m;
|
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end else if (MODE == "DPRAM") begin
|
||||
TRELLIS_RAM16X2 #(
|
||||
.INITVAL_0(permute_initval(LUT0_INITVAL)),
|
||||
|
|
@ -393,17 +418,19 @@ module TRELLIS_SLICE(
|
|||
.DI0(WD0), .DI1(WD1),
|
||||
.WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3),
|
||||
.WRE(WRE), .WCK(WCK),
|
||||
.RAD0(D0), .RAD1(B0), .RAD2(C0), .RAD3(A0),
|
||||
.RAD0(D0m), .RAD1(B0m), .RAD2(C0m), .RAD3(A0m),
|
||||
.DO0(F0), .DO1(F1)
|
||||
);
|
||||
// TODO: confirm RAD and INITVAL ordering
|
||||
// DPRAM mode contract?
|
||||
`ifdef FORMAL
|
||||
always @(*) begin
|
||||
assert(A0==A1);
|
||||
assert(B0==B1);
|
||||
assert(C0==C1);
|
||||
assert(D0==D1);
|
||||
assert(A0m==A1m);
|
||||
assert(B0m==B1m);
|
||||
assert(C0m==C1m);
|
||||
assert(D0m==D1m);
|
||||
end
|
||||
`endif
|
||||
end else begin
|
||||
ERROR_UNKNOWN_SLICE_MODE error();
|
||||
end
|
||||
|
|
@ -455,90 +482,206 @@ module DP16KD(
|
|||
input CSB2, CSB1, CSB0,
|
||||
output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
|
||||
);
|
||||
parameter DATA_WIDTH_A = 18;
|
||||
parameter DATA_WIDTH_B = 18;
|
||||
parameter DATA_WIDTH_A = 18;
|
||||
parameter DATA_WIDTH_B = 18;
|
||||
|
||||
parameter REGMODE_A = "NOREG";
|
||||
parameter REGMODE_B = "NOREG";
|
||||
parameter REGMODE_A = "NOREG";
|
||||
parameter REGMODE_B = "NOREG";
|
||||
|
||||
parameter RESETMODE = "SYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
parameter RESETMODE = "SYNC";
|
||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
||||
|
||||
parameter CSDECODE_A = "0b000";
|
||||
parameter CSDECODE_B = "0b000";
|
||||
parameter CSDECODE_A = "0b000";
|
||||
parameter CSDECODE_B = "0b000";
|
||||
|
||||
parameter WRITEMODE_A = "NORMAL";
|
||||
parameter WRITEMODE_B = "NORMAL";
|
||||
parameter WRITEMODE_A = "NORMAL";
|
||||
parameter WRITEMODE_B = "NORMAL";
|
||||
|
||||
parameter CLKAMUX = "CLKA";
|
||||
parameter CLKBMUX = "CLKB";
|
||||
parameter DIA17MUX = "DIA17";
|
||||
parameter DIA16MUX = "DIA16";
|
||||
parameter DIA15MUX = "DIA15";
|
||||
parameter DIA14MUX = "DIA14";
|
||||
parameter DIA13MUX = "DIA13";
|
||||
parameter DIA12MUX = "DIA12";
|
||||
parameter DIA11MUX = "DIA11";
|
||||
parameter DIA10MUX = "DIA10";
|
||||
parameter DIA9MUX = "DIA9";
|
||||
parameter DIA8MUX = "DIA8";
|
||||
parameter DIA7MUX = "DIA7";
|
||||
parameter DIA6MUX = "DIA6";
|
||||
parameter DIA5MUX = "DIA5";
|
||||
parameter DIA4MUX = "DIA4";
|
||||
parameter DIA3MUX = "DIA3";
|
||||
parameter DIA2MUX = "DIA2";
|
||||
parameter DIA1MUX = "DIA1";
|
||||
parameter DIA0MUX = "DIA0";
|
||||
parameter ADA13MUX = "ADA13";
|
||||
parameter ADA12MUX = "ADA12";
|
||||
parameter ADA11MUX = "ADA11";
|
||||
parameter ADA10MUX = "ADA10";
|
||||
parameter ADA9MUX = "ADA9";
|
||||
parameter ADA8MUX = "ADA8";
|
||||
parameter ADA7MUX = "ADA7";
|
||||
parameter ADA6MUX = "ADA6";
|
||||
parameter ADA5MUX = "ADA5";
|
||||
parameter ADA4MUX = "ADA4";
|
||||
parameter ADA3MUX = "ADA3";
|
||||
parameter ADA2MUX = "ADA2";
|
||||
parameter ADA1MUX = "ADA1";
|
||||
parameter ADA0MUX = "ADA0";
|
||||
parameter CEAMUX = "CEA";
|
||||
parameter OCEAMUX = "OCEA";
|
||||
parameter CLKAMUX = "CLKA";
|
||||
parameter WEAMUX = "WEA";
|
||||
parameter RSTAMUX = "RSTA";
|
||||
parameter CSA2MUX = "CSA2";
|
||||
parameter CSA1MUX = "CSA1";
|
||||
parameter CSA0MUX = "CSA0";
|
||||
parameter DOA17MUX = "DOA17";
|
||||
parameter DOA16MUX = "DOA16";
|
||||
parameter DOA15MUX = "DOA15";
|
||||
parameter DOA14MUX = "DOA14";
|
||||
parameter DOA13MUX = "DOA13";
|
||||
parameter DOA12MUX = "DOA12";
|
||||
parameter DOA11MUX = "DOA11";
|
||||
parameter DOA10MUX = "DOA10";
|
||||
parameter DOA9MUX = "DOA9";
|
||||
parameter DOA8MUX = "DOA8";
|
||||
parameter DOA7MUX = "DOA7";
|
||||
parameter DOA6MUX = "DOA6";
|
||||
parameter DOA5MUX = "DOA5";
|
||||
parameter DOA4MUX = "DOA4";
|
||||
parameter DOA3MUX = "DOA3";
|
||||
parameter DOA2MUX = "DOA2";
|
||||
parameter DOA1MUX = "DOA1";
|
||||
parameter DOA0MUX = "DOA0";
|
||||
parameter DIB17MUX = "DIB17";
|
||||
parameter DIB16MUX = "DIB16";
|
||||
parameter DIB15MUX = "DIB15";
|
||||
parameter DIB14MUX = "DIB14";
|
||||
parameter DIB13MUX = "DIB13";
|
||||
parameter DIB12MUX = "DIB12";
|
||||
parameter DIB11MUX = "DIB11";
|
||||
parameter DIB10MUX = "DIB10";
|
||||
parameter DIB9MUX = "DIB9";
|
||||
parameter DIB8MUX = "DIB8";
|
||||
parameter DIB7MUX = "DIB7";
|
||||
parameter DIB6MUX = "DIB6";
|
||||
parameter DIB5MUX = "DIB5";
|
||||
parameter DIB4MUX = "DIB4";
|
||||
parameter DIB3MUX = "DIB3";
|
||||
parameter DIB2MUX = "DIB2";
|
||||
parameter DIB1MUX = "DIB1";
|
||||
parameter DIB0MUX = "DIB0";
|
||||
parameter ADB13MUX = "ADB13";
|
||||
parameter ADB12MUX = "ADB12";
|
||||
parameter ADB11MUX = "ADB11";
|
||||
parameter ADB10MUX = "ADB10";
|
||||
parameter ADB9MUX = "ADB9";
|
||||
parameter ADB8MUX = "ADB8";
|
||||
parameter ADB7MUX = "ADB7";
|
||||
parameter ADB6MUX = "ADB6";
|
||||
parameter ADB5MUX = "ADB5";
|
||||
parameter ADB4MUX = "ADB4";
|
||||
parameter ADB3MUX = "ADB3";
|
||||
parameter ADB2MUX = "ADB2";
|
||||
parameter ADB1MUX = "ADB1";
|
||||
parameter ADB0MUX = "ADB0";
|
||||
parameter CEBMUX = "CEB";
|
||||
parameter OCEBMUX = "OCEB";
|
||||
parameter CLKBMUX = "CLKB";
|
||||
parameter WEBMUX = "WEB";
|
||||
parameter RSTBMUX = "RSTB";
|
||||
parameter CSB2MUX = "CSB2";
|
||||
parameter CSB1MUX = "CSB1";
|
||||
parameter CSB0MUX = "CSB0";
|
||||
parameter DOB17MUX = "DOB17";
|
||||
parameter DOB16MUX = "DOB16";
|
||||
parameter DOB15MUX = "DOB15";
|
||||
parameter DOB14MUX = "DOB14";
|
||||
parameter DOB13MUX = "DOB13";
|
||||
parameter DOB12MUX = "DOB12";
|
||||
parameter DOB11MUX = "DOB11";
|
||||
parameter DOB10MUX = "DOB10";
|
||||
parameter DOB9MUX = "DOB9";
|
||||
parameter DOB8MUX = "DOB8";
|
||||
parameter DOB7MUX = "DOB7";
|
||||
parameter DOB6MUX = "DOB6";
|
||||
parameter DOB5MUX = "DOB5";
|
||||
parameter DOB4MUX = "DOB4";
|
||||
parameter DOB3MUX = "DOB3";
|
||||
parameter DOB2MUX = "DOB2";
|
||||
parameter DOB1MUX = "DOB1";
|
||||
parameter DOB0MUX = "DOB0";
|
||||
|
||||
parameter GSR = "ENABLED";
|
||||
parameter WID = 0;
|
||||
|
||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter GSR = "ENABLED";
|
||||
|
||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
||||
endmodule
|
||||
|
||||
// TODO: Diamond flip-flops
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ struct DetermineInitPass : public Pass {
|
|||
|
||||
extra_args(args, args.size(), design);
|
||||
|
||||
size_t cnt = 0;
|
||||
int cnt = 0;
|
||||
for (auto module : design->selected_modules())
|
||||
{
|
||||
for (auto cell : module->selected_cells())
|
||||
|
|
@ -65,7 +65,7 @@ struct DetermineInitPass : public Pass {
|
|||
}
|
||||
}
|
||||
}
|
||||
log_header(design, "Updated %lu cells with determined init value.\n", cnt);
|
||||
log_header(design, "Updated %d cells with determined init value.\n", cnt);
|
||||
}
|
||||
} DetermineInitPass;
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,6 @@ OBJS += techlibs/ice40/ice40_braminit.o
|
|||
OBJS += techlibs/ice40/ice40_ffssr.o
|
||||
OBJS += techlibs/ice40/ice40_ffinit.o
|
||||
OBJS += techlibs/ice40/ice40_opt.o
|
||||
OBJS += techlibs/ice40/ice40_unlut.o
|
||||
|
||||
GENFILES += techlibs/ice40/brams_init1.vh
|
||||
GENFILES += techlibs/ice40/brams_init2.vh
|
||||
|
|
|
|||
|
|
@ -44,35 +44,21 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
|
|||
|
||||
genvar i;
|
||||
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
|
||||
`ifdef _ABC
|
||||
\$__ICE40_FULL_ADDER carry (
|
||||
\$__ICE40_CARRY_WRAPPER #(
|
||||
// A[0]: 1010 1010 1010 1010
|
||||
// A[1]: 1100 1100 1100 1100
|
||||
// A[2]: 1111 0000 1111 0000
|
||||
// A[3]: 1111 1111 0000 0000
|
||||
.LUT(16'b 0110_1001_1001_0110)
|
||||
) fadd (
|
||||
.A(AA[i]),
|
||||
.B(BB[i]),
|
||||
.CI(C[i]),
|
||||
.I0(1'b0),
|
||||
.I3(C[i]),
|
||||
.CO(CO[i]),
|
||||
.O(Y[i])
|
||||
);
|
||||
`else
|
||||
SB_CARRY carry (
|
||||
.I0(AA[i]),
|
||||
.I1(BB[i]),
|
||||
.CI(C[i]),
|
||||
.CO(CO[i])
|
||||
);
|
||||
SB_LUT4 #(
|
||||
// I0: 1010 1010 1010 1010
|
||||
// I1: 1100 1100 1100 1100
|
||||
// I2: 1111 0000 1111 0000
|
||||
// I3: 1111 1111 0000 0000
|
||||
.LUT_INIT(16'b 0110_1001_1001_0110)
|
||||
) adder (
|
||||
.I0(1'b0),
|
||||
.I1(AA[i]),
|
||||
.I2(BB[i]),
|
||||
.I3(C[i]),
|
||||
.O(Y[i])
|
||||
);
|
||||
`endif
|
||||
end endgenerate
|
||||
|
||||
assign X = AA ^ BB;
|
||||
|
|
|
|||
|
|
@ -62,26 +62,21 @@ module \$lut (A, Y);
|
|||
endmodule
|
||||
`endif
|
||||
|
||||
`ifdef _ABC
|
||||
module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
|
||||
`ifndef NO_ADDER
|
||||
module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
|
||||
parameter LUT = 0;
|
||||
SB_CARRY carry (
|
||||
.I0(A),
|
||||
.I1(B),
|
||||
.CI(CI),
|
||||
.CO(CO)
|
||||
);
|
||||
SB_LUT4 #(
|
||||
// I0: 1010 1010 1010 1010
|
||||
// I1: 1100 1100 1100 1100
|
||||
// I2: 1111 0000 1111 0000
|
||||
// I3: 1111 1111 0000 0000
|
||||
.LUT_INIT(16'b 0110_1001_1001_0110)
|
||||
) adder (
|
||||
.I0(1'b0),
|
||||
.I1(A),
|
||||
.I2(B),
|
||||
.I3(CI),
|
||||
.O(O)
|
||||
\$lut #(
|
||||
.WIDTH(4),
|
||||
.LUT(LUT)
|
||||
) lut (
|
||||
.A({I0,A,B,I3}),
|
||||
.Y(O)
|
||||
);
|
||||
endmodule
|
||||
`endif
|
||||
|
|
|
|||
|
|
@ -1363,13 +1363,13 @@ module SB_MAC16 (
|
|||
wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
|
||||
wire [15:0] Ah, Al, Bh, Bl;
|
||||
assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
|
||||
assign Al = {A_SIGNED ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
|
||||
assign Al = {A_SIGNED && MODE_8x8 ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
|
||||
assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
|
||||
assign Bl = {B_SIGNED ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
|
||||
assign p_Ah_Bh = Ah * Bh;
|
||||
assign p_Al_Bh = Al * Bh;
|
||||
assign p_Ah_Bl = Ah * Bl;
|
||||
assign p_Al_Bl = Al * Bl;
|
||||
assign Bl = {B_SIGNED && MODE_8x8 ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
|
||||
assign p_Ah_Bh = Ah * Bh; // F
|
||||
assign p_Al_Bh = {8'b0, Al[7:0]} * Bh; // J
|
||||
assign p_Ah_Bl = Ah * {8'b0, Bl[7:0]}; // K
|
||||
assign p_Al_Bl = Al * Bl; // G
|
||||
|
||||
// Regs F and J
|
||||
reg [15:0] rF, rJ;
|
||||
|
|
@ -1400,7 +1400,9 @@ module SB_MAC16 (
|
|||
assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
|
||||
|
||||
// Adder Stage
|
||||
assign iL = iG + (iK << 8) + (iJ << 8) + (iF << 16);
|
||||
wire [23:0] iK_e = {A_SIGNED ? {8{iK[15]}} : 8'b0, iK};
|
||||
wire [23:0] iJ_e = {B_SIGNED ? {8{iJ[15]}} : 8'b0, iJ};
|
||||
assign iL = iG + (iK_e << 8) + (iJ_e << 8) + (iF << 16);
|
||||
|
||||
// Reg H
|
||||
reg [31:0] rH;
|
||||
|
|
|
|||
|
|
@ -69,13 +69,13 @@ static void run_ice40_braminit(Module *module)
|
|||
|
||||
for (int i = 0; i < GetSize(line); i++)
|
||||
{
|
||||
if (in_comment && line.substr(i, 2) == "*/") {
|
||||
if (in_comment && line.compare(i, 2, "*/") == 0) {
|
||||
line[i] = ' ';
|
||||
line[i+1] = ' ';
|
||||
in_comment = false;
|
||||
continue;
|
||||
}
|
||||
if (!in_comment && line.substr(i, 2) == "/*")
|
||||
if (!in_comment && line.compare(i, 2, "/*") == 0)
|
||||
in_comment = true;
|
||||
if (in_comment)
|
||||
line[i] = ' ';
|
||||
|
|
@ -87,7 +87,7 @@ static void run_ice40_braminit(Module *module)
|
|||
long value;
|
||||
|
||||
token = next_token(line, " \t\r\n");
|
||||
if (token.empty() || token.substr(0, 2) == "//")
|
||||
if (token.empty() || token.compare(0, 2, "//") == 0)
|
||||
break;
|
||||
|
||||
if (token[0] == '@') {
|
||||
|
|
|
|||
|
|
@ -117,7 +117,7 @@ static void run_ice40_opts(Module *module)
|
|||
log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
|
||||
log_id(module), log_id(cell), log_signal(replacement_output));
|
||||
cell->type = "$lut";
|
||||
cell->setPort("\\A", { RTLIL::S0, inbit[0], inbit[1], inbit[2] });
|
||||
cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
|
||||
cell->setPort("\\Y", cell->getPort("\\O"));
|
||||
cell->unsetPort("\\B");
|
||||
cell->unsetPort("\\CI");
|
||||
|
|
|
|||
|
|
@ -1,106 +0,0 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "kernel/yosys.h"
|
||||
#include "kernel/sigtools.h"
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
static SigBit get_bit_or_zero(const SigSpec &sig)
|
||||
{
|
||||
if (GetSize(sig) == 0)
|
||||
return State::S0;
|
||||
return sig[0];
|
||||
}
|
||||
|
||||
static void run_ice40_unlut(Module *module)
|
||||
{
|
||||
SigMap sigmap(module);
|
||||
|
||||
for (auto cell : module->selected_cells())
|
||||
{
|
||||
if (cell->type == "\\SB_LUT4")
|
||||
{
|
||||
SigSpec inbits;
|
||||
|
||||
inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
|
||||
inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
|
||||
inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
|
||||
inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
|
||||
sigmap.apply(inbits);
|
||||
|
||||
log("Mapping SB_LUT4 cell %s.%s to $lut.\n", log_id(module), log_id(cell));
|
||||
|
||||
cell->type ="$lut";
|
||||
cell->setParam("\\WIDTH", 4);
|
||||
cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
|
||||
cell->unsetParam("\\LUT_INIT");
|
||||
|
||||
cell->setPort("\\A", SigSpec({
|
||||
get_bit_or_zero(cell->getPort("\\I0")),
|
||||
get_bit_or_zero(cell->getPort("\\I1")),
|
||||
get_bit_or_zero(cell->getPort("\\I2")),
|
||||
get_bit_or_zero(cell->getPort("\\I3"))
|
||||
}));
|
||||
cell->setPort("\\Y", cell->getPort("\\O")[0]);
|
||||
cell->unsetPort("\\I0");
|
||||
cell->unsetPort("\\I1");
|
||||
cell->unsetPort("\\I2");
|
||||
cell->unsetPort("\\I3");
|
||||
cell->unsetPort("\\O");
|
||||
|
||||
cell->check();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
struct Ice40UnlutPass : public Pass {
|
||||
Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SB_LUT4 cells to $lut cells") { }
|
||||
void help() YS_OVERRIDE
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" ice40_unlut [options] [selection]\n");
|
||||
log("\n");
|
||||
log("This command transforms all SB_LUT4 cells to generic $lut cells.\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
{
|
||||
log_header(design, "Executing ICE40_UNLUT pass (convert SB_LUT4 to $lut).\n");
|
||||
log_push();
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
// if (args[argidx] == "-???") {
|
||||
// continue;
|
||||
// }
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
for (auto module : design->selected_modules())
|
||||
run_ice40_unlut(module);
|
||||
}
|
||||
} Ice40UnlutPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
|
@ -183,7 +183,7 @@ struct SynthIce40Pass : public ScriptPass
|
|||
continue;
|
||||
}
|
||||
if (args[argidx] == "-dffe_min_ce_use" && argidx+1 < args.size()) {
|
||||
min_ce_use = std::stoi(args[++argidx]);
|
||||
min_ce_use = atoi(args[++argidx].c_str());
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nobram") {
|
||||
|
|
@ -238,7 +238,7 @@ struct SynthIce40Pass : public ScriptPass
|
|||
{
|
||||
if (check_label("begin"))
|
||||
{
|
||||
run("read_verilog -icells -lib -D_ABC +/ice40/cells_sim.v");
|
||||
run("read_verilog -icells -lib +/ice40/cells_sim.v");
|
||||
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
|
||||
run("proc");
|
||||
}
|
||||
|
|
@ -293,8 +293,10 @@ struct SynthIce40Pass : public ScriptPass
|
|||
{
|
||||
if (nocarry)
|
||||
run("techmap");
|
||||
else
|
||||
run("techmap -map +/techmap.v -map +/ice40/arith_map.v" + std::string(abc == "abc9" ? " -D _ABC" : ""));
|
||||
else {
|
||||
run("ice40_wrapcarry");
|
||||
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
|
||||
}
|
||||
if (retime || help_mode)
|
||||
run(abc + " -dff", "(only if -retime)");
|
||||
run("ice40_opt");
|
||||
|
|
@ -309,7 +311,7 @@ struct SynthIce40Pass : public ScriptPass
|
|||
run("opt_merge");
|
||||
run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
|
||||
}
|
||||
run("techmap -D NO_LUT -map +/ice40/cells_map.v");
|
||||
run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
|
||||
run("opt_expr -mux_undef");
|
||||
run("simplemap");
|
||||
run("ice40_ffinit");
|
||||
|
|
@ -338,13 +340,12 @@ struct SynthIce40Pass : public ScriptPass
|
|||
else
|
||||
wire_delay = 250;
|
||||
run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
|
||||
run("techmap -D NO_LUT -D _ABC -map +/ice40/cells_map.v");
|
||||
}
|
||||
else
|
||||
run(abc + " -dress -lut 4", "(skip if -noabc)");
|
||||
}
|
||||
run("techmap -D NO_LUT -map +/ice40/cells_map.v");
|
||||
run("clean");
|
||||
run("ice40_unlut");
|
||||
run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
read_verilog test_arith.v
|
||||
synth_ice40
|
||||
techmap -map ../cells_sim.v
|
||||
rename test gate
|
||||
|
||||
read_verilog test_arith.v
|
||||
|
|
@ -8,3 +7,11 @@ rename test gold
|
|||
|
||||
miter -equiv -flatten -make_outputs gold gate miter
|
||||
sat -verify -prove trigger 0 -show-ports miter
|
||||
|
||||
synth_ice40 -top gate
|
||||
|
||||
read_verilog test_arith.v
|
||||
rename test gold
|
||||
|
||||
miter -equiv -flatten -make_outputs gold gate miter
|
||||
sat -verify -prove trigger 0 -show-ports miter
|
||||
|
|
|
|||
|
|
@ -1,10 +1,15 @@
|
|||
#!/bin/bash
|
||||
set -ex
|
||||
sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
|
||||
cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
|
||||
if [ ! -f "test_dsp_model_ref.v" ]; then
|
||||
cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
|
||||
fi
|
||||
for tb in testbench \
|
||||
testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \
|
||||
testbench_seq_16x16_A testbench_seq_16x16_B
|
||||
testbench_seq_16x16_A testbench_seq_16x16_B \
|
||||
testbench_comb_8x8_A_signedA testbench_comb_8x8_A_signedB testbench_comb_8x8_A_signedAB \
|
||||
testbench_comb_8x8_B_signedA testbench_comb_8x8_B_signedB testbench_comb_8x8_B_signedAB \
|
||||
testbench_comb_16x16_signedA testbench_comb_16x16_signedB testbench_comb_16x16_signedAB
|
||||
do
|
||||
iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
|
||||
vvp -N ./test_dsp_model
|
||||
|
|
|
|||
|
|
@ -241,6 +241,81 @@ module testbench_comb_8x8_A;
|
|||
) testbench ();
|
||||
endmodule
|
||||
|
||||
module testbench_comb_8x8_A_signedA;
|
||||
testbench #(
|
||||
.NEG_TRIGGER (0),
|
||||
.C_REG (0),
|
||||
.A_REG (0),
|
||||
.B_REG (0),
|
||||
.D_REG (0),
|
||||
.TOP_8x8_MULT_REG (0),
|
||||
.BOT_8x8_MULT_REG (0),
|
||||
.PIPELINE_16x16_MULT_REG1 (0),
|
||||
.PIPELINE_16x16_MULT_REG2 (0),
|
||||
.TOPOUTPUT_SELECT (2), // 0=P, 1=Q, 2=8x8, 3=16x16
|
||||
.TOPADDSUB_LOWERINPUT (0), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
|
||||
.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.BOTOUTPUT_SELECT (2), // 0=R, 1=S, 2=8x8, 3=16x16
|
||||
.BOTADDSUB_LOWERINPUT (0), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
|
||||
.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.MODE_8x8 (0),
|
||||
.A_SIGNED (1),
|
||||
.B_SIGNED (0)
|
||||
) testbench ();
|
||||
endmodule
|
||||
|
||||
module testbench_comb_8x8_A_signedB;
|
||||
testbench #(
|
||||
.NEG_TRIGGER (0),
|
||||
.C_REG (0),
|
||||
.A_REG (0),
|
||||
.B_REG (0),
|
||||
.D_REG (0),
|
||||
.TOP_8x8_MULT_REG (0),
|
||||
.BOT_8x8_MULT_REG (0),
|
||||
.PIPELINE_16x16_MULT_REG1 (0),
|
||||
.PIPELINE_16x16_MULT_REG2 (0),
|
||||
.TOPOUTPUT_SELECT (2), // 0=P, 1=Q, 2=8x8, 3=16x16
|
||||
.TOPADDSUB_LOWERINPUT (0), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
|
||||
.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.BOTOUTPUT_SELECT (2), // 0=R, 1=S, 2=8x8, 3=16x16
|
||||
.BOTADDSUB_LOWERINPUT (0), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
|
||||
.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.MODE_8x8 (0),
|
||||
.A_SIGNED (0),
|
||||
.B_SIGNED (1)
|
||||
) testbench ();
|
||||
endmodule
|
||||
|
||||
module testbench_comb_8x8_A_signedAB;
|
||||
testbench #(
|
||||
.NEG_TRIGGER (0),
|
||||
.C_REG (0),
|
||||
.A_REG (0),
|
||||
.B_REG (0),
|
||||
.D_REG (0),
|
||||
.TOP_8x8_MULT_REG (0),
|
||||
.BOT_8x8_MULT_REG (0),
|
||||
.PIPELINE_16x16_MULT_REG1 (0),
|
||||
.PIPELINE_16x16_MULT_REG2 (0),
|
||||
.TOPOUTPUT_SELECT (2), // 0=P, 1=Q, 2=8x8, 3=16x16
|
||||
.TOPADDSUB_LOWERINPUT (0), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.TOPADDSUB_UPPERINPUT (0), // 0=Q, 1=C
|
||||
.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.BOTOUTPUT_SELECT (2), // 0=R, 1=S, 2=8x8, 3=16x16
|
||||
.BOTADDSUB_LOWERINPUT (0), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.BOTADDSUB_UPPERINPUT (0), // 0=S, 1=D
|
||||
.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.MODE_8x8 (0),
|
||||
.A_SIGNED (1),
|
||||
.B_SIGNED (1)
|
||||
) testbench ();
|
||||
endmodule
|
||||
|
||||
module testbench_comb_8x8_B;
|
||||
testbench #(
|
||||
.NEG_TRIGGER (0),
|
||||
|
|
@ -266,6 +341,81 @@ module testbench_comb_8x8_B;
|
|||
) testbench ();
|
||||
endmodule
|
||||
|
||||
module testbench_comb_8x8_B_signedA;
|
||||
testbench #(
|
||||
.NEG_TRIGGER (0),
|
||||
.C_REG (0),
|
||||
.A_REG (0),
|
||||
.B_REG (0),
|
||||
.D_REG (0),
|
||||
.TOP_8x8_MULT_REG (0),
|
||||
.BOT_8x8_MULT_REG (0),
|
||||
.PIPELINE_16x16_MULT_REG1 (0),
|
||||
.PIPELINE_16x16_MULT_REG2 (0),
|
||||
.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
|
||||
.TOPADDSUB_LOWERINPUT (1), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
|
||||
.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
|
||||
.BOTADDSUB_LOWERINPUT (1), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
|
||||
.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.MODE_8x8 (0),
|
||||
.A_SIGNED (1),
|
||||
.B_SIGNED (0)
|
||||
) testbench ();
|
||||
endmodule
|
||||
|
||||
module testbench_comb_8x8_B_signedB;
|
||||
testbench #(
|
||||
.NEG_TRIGGER (0),
|
||||
.C_REG (0),
|
||||
.A_REG (0),
|
||||
.B_REG (0),
|
||||
.D_REG (0),
|
||||
.TOP_8x8_MULT_REG (0),
|
||||
.BOT_8x8_MULT_REG (0),
|
||||
.PIPELINE_16x16_MULT_REG1 (0),
|
||||
.PIPELINE_16x16_MULT_REG2 (0),
|
||||
.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
|
||||
.TOPADDSUB_LOWERINPUT (1), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
|
||||
.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
|
||||
.BOTADDSUB_LOWERINPUT (1), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
|
||||
.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.MODE_8x8 (0),
|
||||
.A_SIGNED (0),
|
||||
.B_SIGNED (1)
|
||||
) testbench ();
|
||||
endmodule
|
||||
|
||||
module testbench_comb_8x8_B_signedAB;
|
||||
testbench #(
|
||||
.NEG_TRIGGER (0),
|
||||
.C_REG (0),
|
||||
.A_REG (0),
|
||||
.B_REG (0),
|
||||
.D_REG (0),
|
||||
.TOP_8x8_MULT_REG (0),
|
||||
.BOT_8x8_MULT_REG (0),
|
||||
.PIPELINE_16x16_MULT_REG1 (0),
|
||||
.PIPELINE_16x16_MULT_REG2 (0),
|
||||
.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
|
||||
.TOPADDSUB_LOWERINPUT (1), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
|
||||
.TOPADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
|
||||
.BOTADDSUB_LOWERINPUT (1), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
|
||||
.BOTADDSUB_CARRYSELECT (0), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.MODE_8x8 (0),
|
||||
.A_SIGNED (1),
|
||||
.B_SIGNED (1)
|
||||
) testbench ();
|
||||
endmodule
|
||||
|
||||
module testbench_comb_16x16;
|
||||
testbench #(
|
||||
.NEG_TRIGGER (0),
|
||||
|
|
@ -291,6 +441,81 @@ module testbench_comb_16x16;
|
|||
) testbench ();
|
||||
endmodule
|
||||
|
||||
module testbench_comb_16x16_signedA;
|
||||
testbench #(
|
||||
.NEG_TRIGGER (0),
|
||||
.C_REG (0),
|
||||
.A_REG (0),
|
||||
.B_REG (0),
|
||||
.D_REG (0),
|
||||
.TOP_8x8_MULT_REG (0),
|
||||
.BOT_8x8_MULT_REG (0),
|
||||
.PIPELINE_16x16_MULT_REG1 (0),
|
||||
.PIPELINE_16x16_MULT_REG2 (0),
|
||||
.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
|
||||
.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
|
||||
.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
|
||||
.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
|
||||
.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.MODE_8x8 (0),
|
||||
.A_SIGNED (1),
|
||||
.B_SIGNED (0)
|
||||
) testbench ();
|
||||
endmodule
|
||||
|
||||
module testbench_comb_16x16_signedB;
|
||||
testbench #(
|
||||
.NEG_TRIGGER (0),
|
||||
.C_REG (0),
|
||||
.A_REG (0),
|
||||
.B_REG (0),
|
||||
.D_REG (0),
|
||||
.TOP_8x8_MULT_REG (0),
|
||||
.BOT_8x8_MULT_REG (0),
|
||||
.PIPELINE_16x16_MULT_REG1 (0),
|
||||
.PIPELINE_16x16_MULT_REG2 (0),
|
||||
.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
|
||||
.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
|
||||
.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
|
||||
.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
|
||||
.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.MODE_8x8 (0),
|
||||
.A_SIGNED (0),
|
||||
.B_SIGNED (1)
|
||||
) testbench ();
|
||||
endmodule
|
||||
|
||||
module testbench_comb_16x16_signedAB;
|
||||
testbench #(
|
||||
.NEG_TRIGGER (0),
|
||||
.C_REG (0),
|
||||
.A_REG (0),
|
||||
.B_REG (0),
|
||||
.D_REG (0),
|
||||
.TOP_8x8_MULT_REG (0),
|
||||
.BOT_8x8_MULT_REG (0),
|
||||
.PIPELINE_16x16_MULT_REG1 (0),
|
||||
.PIPELINE_16x16_MULT_REG2 (0),
|
||||
.TOPOUTPUT_SELECT (0), // 0=P, 1=Q, 2=8x8, 3=16x16
|
||||
.TOPADDSUB_LOWERINPUT (2), // 0=A, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.TOPADDSUB_UPPERINPUT (1), // 0=Q, 1=C
|
||||
.TOPADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.BOTOUTPUT_SELECT (0), // 0=R, 1=S, 2=8x8, 3=16x16
|
||||
.BOTADDSUB_LOWERINPUT (2), // 0=B, 1=8x8, 2=16x16, 3=S-EXT
|
||||
.BOTADDSUB_UPPERINPUT (1), // 0=S, 1=D
|
||||
.BOTADDSUB_CARRYSELECT (2), // 0=0, 1=1, 2=ACI, 3=CI
|
||||
.MODE_8x8 (0),
|
||||
.A_SIGNED (1),
|
||||
.B_SIGNED (1)
|
||||
) testbench ();
|
||||
endmodule
|
||||
|
||||
module testbench_seq_16x16_A;
|
||||
testbench #(
|
||||
.NEG_TRIGGER (0),
|
||||
|
|
|
|||
|
|
@ -3,22 +3,12 @@ OBJS += techlibs/intel/synth_intel.o
|
|||
|
||||
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v))
|
||||
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v))
|
||||
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams.txt))
|
||||
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map.v))
|
||||
$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_sim.v))
|
||||
$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_map.v))
|
||||
$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_map.v))
|
||||
$(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_map.v))
|
||||
$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_map.v))
|
||||
$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_map.v))
|
||||
$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_map.v))
|
||||
#$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/arith_map.v))
|
||||
#$(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/arith_map.v))
|
||||
#$(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/arith_map.v))
|
||||
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt))
|
||||
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v))
|
||||
|
||||
# Add the cell models and mappings for the VQM backend
|
||||
families := max10 a10gx cyclonev cyclone10 cycloneiv cycloneive
|
||||
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v)))
|
||||
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v)))
|
||||
#$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v))
|
||||
|
||||
|
|
|
|||
|
|
@ -61,8 +61,8 @@ struct SynthIntelPass : public ScriptPass {
|
|||
log(" from label is synonymous to 'begin', and empty to label is\n");
|
||||
log(" synonymous to the end of the command list.\n");
|
||||
log("\n");
|
||||
log(" -noiopads\n");
|
||||
log(" do not use IO pad cells in output netlist\n");
|
||||
log(" -iopads\n");
|
||||
log(" use IO pad cells in output netlist\n");
|
||||
log("\n");
|
||||
log(" -nobram\n");
|
||||
log(" do not use block RAM cells in output netlist\n");
|
||||
|
|
@ -79,7 +79,7 @@ struct SynthIntelPass : public ScriptPass {
|
|||
}
|
||||
|
||||
string top_opt, family_opt, vout_file, blif_file;
|
||||
bool retime, flatten, nobram, noiopads;
|
||||
bool retime, flatten, nobram, iopads;
|
||||
|
||||
void clear_flags() YS_OVERRIDE
|
||||
{
|
||||
|
|
@ -90,7 +90,7 @@ struct SynthIntelPass : public ScriptPass {
|
|||
retime = false;
|
||||
flatten = true;
|
||||
nobram = false;
|
||||
noiopads = false;
|
||||
iopads = false;
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
|
|
@ -125,8 +125,8 @@ struct SynthIntelPass : public ScriptPass {
|
|||
run_to = args[argidx].substr(pos + 1);
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-noiopads") {
|
||||
noiopads = true;
|
||||
if (args[argidx] == "-iopads") {
|
||||
iopads = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nobram") {
|
||||
|
|
@ -187,8 +187,15 @@ struct SynthIntelPass : public ScriptPass {
|
|||
}
|
||||
|
||||
if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
|
||||
run("memory_bram -rules +/intel/common/brams.txt");
|
||||
run("techmap -map +/intel/common/brams_map.v");
|
||||
if (family_opt == "cycloneiv" ||
|
||||
family_opt == "cycloneive" ||
|
||||
family_opt == "max10" ||
|
||||
help_mode) {
|
||||
run("memory_bram -rules +/intel/common/brams_m9k.txt", "(if applicable for family)");
|
||||
run("techmap -map +/intel/common/brams_map_m9k.v", "(if applicable for family)");
|
||||
} else {
|
||||
log_warning("BRAM mapping is not currently supported for %s.\n", family_opt.c_str());
|
||||
}
|
||||
}
|
||||
|
||||
if (check_label("map_ffram")) {
|
||||
|
|
@ -215,10 +222,9 @@ struct SynthIntelPass : public ScriptPass {
|
|||
}
|
||||
|
||||
if (check_label("map_cells")) {
|
||||
if (!noiopads)
|
||||
run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
|
||||
if (iopads || help_mode)
|
||||
run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(if -iopads)");
|
||||
run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
|
||||
|
||||
run("dffinit -highlow -ff dffeas q power_up");
|
||||
run("clean -purge");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,9 +24,9 @@ module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLA
|
|||
(* techmap_celltype = "$_DFF_PN0_" *)
|
||||
module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
|
||||
(* techmap_celltype = "$_DFF_NN1_" *)
|
||||
module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
|
||||
module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
|
||||
(* techmap_celltype = "$_DFF_PN1_" *)
|
||||
module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
|
||||
module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
|
||||
|
||||
module \$__SHREG_ (input C, input D, input E, output Q);
|
||||
parameter DEPTH = 0;
|
||||
|
|
|
|||
|
|
@ -195,7 +195,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
continue;
|
||||
}
|
||||
if (args[argidx] == "-widemux" && argidx+1 < args.size()) {
|
||||
widemux = std::stoi(args[++argidx]);
|
||||
widemux = atoi(args[++argidx].c_str());
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-abc9") {
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@ module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT
|
|||
.CLKBRDCLK(CLK2 ^ !CLKPOL2),
|
||||
.ENBRDEN(A1EN),
|
||||
.REGCEBREGCE(|1),
|
||||
.RSTB(|0)
|
||||
.RSTBRST(|0)
|
||||
);
|
||||
endmodule
|
||||
|
||||
|
|
@ -217,7 +217,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT
|
|||
.CLKBRDCLK(CLK3 ^ !CLKPOL3),
|
||||
.ENBRDEN(|1),
|
||||
.REGCEBREGCE(|0),
|
||||
.RSTB(|0),
|
||||
.RSTBRST(|0),
|
||||
.WEBWEU(B1EN_2)
|
||||
);
|
||||
end else begin
|
||||
|
|
@ -248,7 +248,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT
|
|||
.CLKBRDCLK(CLK3 ^ !CLKPOL3),
|
||||
.ENBRDEN(|1),
|
||||
.REGCEBREGCE(|0),
|
||||
.RSTB(|0),
|
||||
.RSTBRST(|0),
|
||||
.WEBWEU(B1EN_2)
|
||||
);
|
||||
end endgenerate
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue