1853 commits

Author	SHA1	Message	Date
Akash Levy	c8f7441a4a	Fix skip default value	2024-06-05 09:33:03 -07:00
Akash Levy	c59a997255	Ignore files properly	2024-06-05 07:53:21 -07:00
Akash Levy	4d44099d09	Support for ignoring translate_off and ignoring files	2024-06-05 05:00:05 -07:00
Akash Levy	5dc62bec0b	Support .inc files and readmemh missing file	2024-06-03 20:05:30 -07:00
Akash Levy	92e44cc9a3	Minor fix to ignore files	2024-06-03 18:17:50 -07:00
Akash Levy	4339b3681a	Elaborate top level modules undo	2024-06-03 16:17:51 -07:00
Akash Levy	a692bf17d7	Improper ignore translates	2024-06-03 11:23:16 -07:00
Akash Levy	783c0a593a	Actually optimize with Verific now	2024-06-03 04:55:47 -07:00
Akash Levy	4475b50ffa	Undo some ugly stuff and make more attempted fixes	2024-06-02 23:33:23 -07:00
Akash Levy	2585636d18	Use ability to get/set IMPORT runtime flags	2024-06-02 22:24:29 -07:00
Akash Levy	28a03380b7	Priority selector fixes (opt order), relaxed checking, warning if using Yosys case statements	2024-06-02 18:45:31 -07:00
Akash Levy	85cbd05bb1	Update some runtime flags to fix some potential issues	2024-06-02 01:12:43 -07:00
Akash Levy	5bc23b272a	Add blackboxes a little later and use ignore files rather than ignore modules	2024-05-30 14:17:10 -07:00
Akash Levy	8b93aa10cb	Add leakage power unit support	2024-05-29 23:43:47 -07:00
Akash Levy	a55a4d461e	Infer wide operators pre elaboration (post does not work as well!)	2024-05-28 04:39:29 -07:00
Akash Levy	4062825a9e	Disable Liberty support, add blackbox Verilog module, and add attribute parsing into Yosys Liberty parser	2024-05-28 01:47:46 -07:00
Akash Levy	b90c20cd14	Update Verific, add opt to hierarchy pass, make opt run a bunch of Verific optimizations, update some Verific runtime flags	2024-05-27 21:56:08 -07:00
Akash Levy	a98fcbd48b	Revert Verific flags	2024-05-25 23:21:31 -07:00
Akash Levy	60ce37c2bd	Don't reenable verific, move to c_cpp_properties.json in .vscode	2024-05-24 01:49:54 -07:00
Akash Levy	22bdf4035a	Verific to handle all RAMs	2024-05-24 01:08:37 -07:00
Akash Levy	6300c491ea	Update Yosys runtime flags for Verific to remove multi-port memory support	2024-05-24 00:26:37 -07:00
Akash Levy	66eabb1d2c	Define SYNTH and OVL_SVA by default	2024-05-23 21:05:57 -07:00
Akash Levy	187737b86a	Don't adjust naming on imported cells. Add $ for each pass	2024-05-19 15:02:40 -07:00
Akash Levy	60e598b9c8	Define SYNTHESIS earlier and in both, support ignored module specification	2024-05-17 04:46:28 -07:00
Akash Levy	375f73bbce	Update for Amba support	2024-05-15 15:37:14 -07:00
Akash Levy	ed42470d45	Move ignore translate up here and update verificc	2024-05-14 16:02:33 -07:00
Akash Levy	81b542fd31	Updated to support Amba comments and .h files	2024-05-14 13:25:43 -07:00
Akash Levy	667c3375e8	Macro defines don't pass or succeed the same way	2024-05-13 15:53:54 -07:00
Akash Levy	fb182d10d6	Update formats to include .svh	2024-05-13 00:00:49 -07:00
Akash Levy	ba5b12ae0c	Don't include source in name	2024-05-11 23:14:39 -07:00
Akash Levy	36f9c50c03	Add mode for nested capital F file	2024-05-11 12:53:33 -07:00
Akash Levy	a7e1dcef12	Move register file to after registering directories, also rename to AUTO-DISCOVER	2024-05-10 12:44:36 -07:00
Akash Levy	fb55287a3b	Add SVP extension, log auto-discovery, support gzip in verific	2024-05-10 11:09:22 -07:00
Akash Levy	c7f66737aa	Fix Yosys to allow SV again	2024-05-09 06:36:02 -07:00
Akash Levy	da8c1955af	Updates from YosysHQ	2024-05-09 05:10:44 -07:00
Akash Levy	8841cc4d76	Copy all info from .f file to hdl_file_sort for better auto-discovery	2024-05-09 04:54:57 -07:00
Akash Levy	b5af9b9a8a	Fix SystemVerilog support for .v files	2024-05-09 04:54:00 -07:00
Akash Levy	47b6738124	Add -auto_discover to import	2024-05-08 04:21:30 -07:00
Akash Levy	2e21078a83	Merge branch 'YosysHQ:main' into master	2024-05-07 18:21:19 -07:00
Krystine Sherwin	df95ea824b	read_verilog: Add missing defaults for flags ... Fix for YosysHQ/sby#103	2024-05-07 20:25:36 +02:00
Akash Levy	8c330c0e4b	Merge branch 'YosysHQ:main' into master	2024-04-29 22:22:47 -07:00
George Rennie	4e6deb53b6	read_aiger: Fix incorrect read of binary Aiger without outputs ... * Also makes all ascii parsing finish reading lines and adds a small test	2024-04-29 14:06:58 +01:00
Akash Levy	45b723d6f3	Merge branch 'YosysHQ:main' into master	2024-04-25 06:24:57 -07:00
KrystalDelusion	c3ae33da33	Merge pull request #4285 from YosysHQ/typo_fixup ... Typo fixing	2024-04-25 09:54:48 +12:00
Akash Levy	3945e6ecff	Merge branch 'YosysHQ:main' into master	2024-04-16 10:59:45 -07:00
Miodrag Milanovic	af94123730	verific: expose library name as module attribute	2024-04-15 17:01:07 +02:00
Akash Levy	6a3bb58d5d	Updates from yosys	2024-04-14 18:53:44 -07:00
N. Engelhardt	3d5e23e585	Merge pull request #4302 from YosysHQ/vhdl_2019 ... Verific support for VHDL 2019	2024-04-09 18:25:05 +02:00
N. Engelhardt	18afa36acd	Merge pull request #4273 from YosysHQ/vhdl_params ... verific: Improve import VHDL constants	2024-04-09 18:01:41 +02:00
Akash Levy	29e9d3ea92	Updates for hiding verific	2024-04-09 07:16:22 -07:00