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https://github.com/YosysHQ/yosys
synced 2025-04-23 00:55:32 +00:00
Undo some ugly stuff and make more attempted fixes
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parent
ad1197d5ad
commit
4475b50ffa
4 changed files with 7 additions and 15 deletions
2
Makefile
2
Makefile
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@ -18,8 +18,6 @@ ENABLE_GHDL := 0
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ENABLE_VERIFIC := 1
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ENABLE_VERIFIC_EDIF := 0
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ENABLE_VERIFIC_LIBERTY := 0
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# ENABLE_VERIFIC_YOSYSHQ := 0
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# ENABLE_VERIFIC_SILIMATE := 1
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DISABLE_VERIFIC_EXTENSIONS := 1
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DISABLE_VERIFIC_VHDL := 1
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ENABLE_COVER := 0
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@ -1195,9 +1195,6 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
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if (inst->Type() == OPER_WIDE_CASE_SELECT_BOX)
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{
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// SILIMATE: WARN FOR THIS CASE BECAUSE YOSYS CAN DO WHATEVER IT WANTS
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log_warning("Using OPER_WIDE_CASE_SELECT_BOX! This could result in long chains of logic...\n");
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RTLIL::SigSpec sig_out_val = operatorInport(inst, "out_value");
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RTLIL::SigSpec sig_select = operatorInport(inst, "select");
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RTLIL::SigSpec sig_select_values = operatorInportCase(inst, "select_values");
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@ -2776,9 +2773,6 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
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log(" Removing buffers for %s.\n", nl.first.c_str());
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nl.second->RemoveBuffers();
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log(" Optimizing priority selectors for %s.\n", nl.first.c_str());
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nl.second->OptimizePrioSelectors();
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log(" Balancing timing for %s.\n", nl.first.c_str());
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unsigned result = nl.second->BalanceTiming(0);
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log(" Balance timing result before: %d\n", result);
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@ -2788,10 +2782,9 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
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log(" Running post-elaboration for %s.\n", nl.first.c_str());
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nl.second->PostElaborationProcess();
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log(" Optimizing priority selectors for %s.\n", nl.first.c_str());
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nl.second->OptimizePrioSelectors();
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log(" Merging selectors for %s.\n", nl.first.c_str());
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nl.second->MergeSelectors();
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log(" Running operator optimization for %s.\n", nl.first.c_str());
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nl.second->OperatorOptimization(1, 1);
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log(" Performing resource sharing for %s.\n", nl.first.c_str());
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nl.second->ResourceSharing();
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log(" Performing final resource merging for %s.\n", nl.first.c_str());
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@ -2803,6 +2796,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
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nl.second->MergeRams();
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log(" Balancing timing for %s.\n", nl.first.c_str());
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result = nl.second->BalanceTiming(0);
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log(" Balance timing result before: %d\n", result);
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result = nl.second->BalanceTiming(1);
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log(" Balance timing result after: %d\n", result);
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@ -195,8 +195,8 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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for (auto &operand : muxed_operands) {
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operand.sig.extend_u0(max_width, operand.is_signed);
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// if (operand.sign != muxed_operands[0].sign)
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// operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed));
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if (operand.sign != muxed_operands[0].sign)
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operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed));
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}
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for (const auto& p : ports) {
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2
verific
2
verific
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@ -1 +1 @@
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Subproject commit 44a6fdd9f1017959ffd53dafdca75904e5230224
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Subproject commit 5494ec6005899a889b603216e5f7a9ea58dee712
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