3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00

Undo some ugly stuff and make more attempted fixes

This commit is contained in:
Akash Levy 2024-06-02 23:33:23 -07:00
parent ad1197d5ad
commit 4475b50ffa
4 changed files with 7 additions and 15 deletions

View file

@ -18,8 +18,6 @@ ENABLE_GHDL := 0
ENABLE_VERIFIC := 1
ENABLE_VERIFIC_EDIF := 0
ENABLE_VERIFIC_LIBERTY := 0
# ENABLE_VERIFIC_YOSYSHQ := 0
# ENABLE_VERIFIC_SILIMATE := 1
DISABLE_VERIFIC_EXTENSIONS := 1
DISABLE_VERIFIC_VHDL := 1
ENABLE_COVER := 0

View file

@ -1195,9 +1195,6 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
if (inst->Type() == OPER_WIDE_CASE_SELECT_BOX)
{
// SILIMATE: WARN FOR THIS CASE BECAUSE YOSYS CAN DO WHATEVER IT WANTS
log_warning("Using OPER_WIDE_CASE_SELECT_BOX! This could result in long chains of logic...\n");
RTLIL::SigSpec sig_out_val = operatorInport(inst, "out_value");
RTLIL::SigSpec sig_select = operatorInport(inst, "select");
RTLIL::SigSpec sig_select_values = operatorInportCase(inst, "select_values");
@ -2776,9 +2773,6 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
log(" Removing buffers for %s.\n", nl.first.c_str());
nl.second->RemoveBuffers();
log(" Optimizing priority selectors for %s.\n", nl.first.c_str());
nl.second->OptimizePrioSelectors();
log(" Balancing timing for %s.\n", nl.first.c_str());
unsigned result = nl.second->BalanceTiming(0);
log(" Balance timing result before: %d\n", result);
@ -2788,10 +2782,9 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
log(" Running post-elaboration for %s.\n", nl.first.c_str());
nl.second->PostElaborationProcess();
log(" Optimizing priority selectors for %s.\n", nl.first.c_str());
nl.second->OptimizePrioSelectors();
log(" Merging selectors for %s.\n", nl.first.c_str());
nl.second->MergeSelectors();
log(" Running operator optimization for %s.\n", nl.first.c_str());
nl.second->OperatorOptimization(1, 1);
log(" Performing resource sharing for %s.\n", nl.first.c_str());
nl.second->ResourceSharing();
log(" Performing final resource merging for %s.\n", nl.first.c_str());
@ -2803,6 +2796,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
nl.second->MergeRams();
log(" Balancing timing for %s.\n", nl.first.c_str());
result = nl.second->BalanceTiming(0);
log(" Balance timing result before: %d\n", result);
result = nl.second->BalanceTiming(1);
log(" Balance timing result after: %d\n", result);

View file

@ -195,8 +195,8 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
for (auto &operand : muxed_operands) {
operand.sig.extend_u0(max_width, operand.is_signed);
// if (operand.sign != muxed_operands[0].sign)
// operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed));
if (operand.sign != muxed_operands[0].sign)
operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed));
}
for (const auto& p : ports) {

@ -1 +1 @@
Subproject commit 44a6fdd9f1017959ffd53dafdca75904e5230224
Subproject commit 5494ec6005899a889b603216e5f7a9ea58dee712