mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity
7873 commits 124 branches 59 tags 44 MiB
Commit graph

825 commits

Author SHA1 Message Date
Eddie Hung
8c813632b6 Revert "submod to bitty rather bussy, for bussy wires used as input and output" 
This reverts commit cba3073026.
 2019-11-27 00:48:22 -08:00
Eddie Hung
6318e3ce6d Fix wire width 2019-11-26 23:38:49 -08:00
Eddie Hung
dd317c9280 Add testcase where \init is copied 2019-11-25 16:07:35 -08:00
Eddie Hung
5cd3d3db0a Remove redundant flatten 2019-11-22 22:28:10 -08:00
Eddie Hung
08f85e6438 Stray dump 2019-11-22 20:53:48 -08:00
Eddie Hung
4fdcf8f7d7 Add another test with constant driver 2019-11-22 17:23:34 -08:00
Eddie Hung
8779faf789 Cleanup spacing 2019-11-22 16:50:09 -08:00
Eddie Hung
2ef2e2c040 Add testcase 2019-11-22 16:48:11 -08:00
Clifford Wolf
72d2ef6fd0
Merge pull request #1511 from YosysHQ/dave/always 
sv: Error checking for always_comb, always_latch and always_ff
 2019-11-22 15:32:29 +01:00
Marcin Kościelnicki
e110df9c48 gowin: Remove show command from tests. 2019-11-22 14:49:35 +01:00
David Shah
49b670ca38 sv: Add tests for SV always types 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-21 21:06:28 +00:00
Clifford Wolf
7ea0a5937b
Merge pull request #1449 from pepijndevos/gowin 
Improvements for gowin support
 2019-11-19 17:29:27 +01:00
Marcin Kościelnicki
15232a48af Fix #1462, #1480. 2019-11-19 08:57:39 +01:00
Marcin Kościelnicki
38e72d6e13 Fix #1496. 2019-11-18 04:16:48 +01:00
Pepijn de Vos
32f0296df1 Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin 2019-11-16 12:43:17 +01:00
Pepijn de Vos
ab8c521030 fix fsm test with proper clock enable polarity 2019-11-11 17:51:26 +01:00
Miodrag Milanovic
3e0ffe05a7 Fixed tests 2019-11-11 15:41:33 +01:00
Pepijn de Vos
0e5dbc4abc fix wide luts 2019-11-06 19:48:18 +01:00
Pepijn de Vos
df8390f5df don't cound exact luts in big muxes; futile and fragile 2019-10-30 14:58:25 +01:00
Pepijn de Vos
903f997391 add tristate buffer and test 2019-10-28 15:18:01 +01:00
Pepijn de Vos
9517525224 do not use wide luts in testcase 2019-10-28 14:40:12 +01:00
Pepijn de Vos
8226f2db0b ALU sim tweaks 2019-10-24 13:39:43 +02:00
Pepijn de Vos
83fbfe0964 Add some tests 
Copied from Efinix.

* fsm is broken
* latch and tribuf are not implemented yet
* memory maps to dram
 2019-10-21 16:25:15 +02:00
Miodrag Milanovic
190b40341a fixed error 2019-10-18 13:15:36 +02:00
Miodrag Milanovic
9bd9db56c8 Unify verilog style 2019-10-18 12:50:24 +02:00
Miodrag Milanovic
12383f37b2 Common memory test now shared 2019-10-18 12:33:35 +02:00
Miodrag Milanovic
477702b8c9 Remove not needed tests 2019-10-18 12:20:35 +02:00
Miodrag Milanovic
5603595e5c Share common tests 2019-10-18 12:19:59 +02:00
Miodrag Milanovic
ab98f2dccf fix yosys path 2019-10-18 11:18:53 +02:00
Miodrag Milanovic
56f9482675 Fix path to yosys 2019-10-18 11:12:03 +02:00
Miodrag Milanovic
c2ec7ca703 Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
Miodrag Milanovic
3c41599ee1 Add async2sync 2019-10-18 11:00:27 +02:00
Miodrag Milanović
b4d7650548
Merge branch 'master' into mmicko/efinix 2019-10-18 10:54:28 +02:00
Miodrag Milanović
66fca65b58
Merge branch 'master' into mmicko/anlogic 2019-10-18 10:53:56 +02:00
Miodrag Milanović
0b0b0cc0d9
Merge branch 'master' into eddie/pr1352 2019-10-18 10:52:50 +02:00
Miodrag Milanovic
b659082e4a hierarchy - proc reorder 2019-10-18 09:13:06 +02:00
Miodrag Milanovic
46af9a0ff7 hierarchy - proc reorder 2019-10-18 09:06:43 +02:00
Miodrag Milanovic
0d60902fd9 hierarchy - proc reorder 2019-10-18 09:04:02 +02:00
Miodrag Milanovic
e6ad714d20 hierarchy - proc reorder 2019-10-18 08:06:57 +02:00
Miodrag Milanovic
980df499ab Make equivalence work with latest master 2019-10-17 17:24:53 +02:00
Miodrag Milanovic
b2f0d75807 remove not needed top module 2019-10-17 17:11:11 +02:00
Miodrag Milanovic
1a399c6456 remove not needed top module 2019-10-17 17:11:11 +02:00
Miodrag Milanovic
a198bcdd4f split muxes synth per type 2019-10-17 17:11:11 +02:00
Miodrag Milanovic
36af102801 Test dffs separetely 2019-10-17 17:11:11 +02:00
Miodrag Milanovic
487b38b124 Split latches into separete tests 2019-10-17 17:11:11 +02:00
Miodrag Milanovic
fba6229718 Fix formatting 2019-10-17 17:10:42 +02:00
Miodrag Milanovic
53bc499a90 Clean verilog code from not used define block 2019-10-17 17:10:42 +02:00
Miodrag Milanovic
d37cd267a5 Removed alu and div_mod test as agreed, ignore generated files 2019-10-17 17:10:42 +02:00
Miodrag Milanovic
a7fbc8c3fe Test per flip-flop type 2019-10-17 17:10:42 +02:00
Eddie Hung
3b44084320 Add -assert 2019-10-17 17:10:42 +02:00