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Test per flip-flop type

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This commit is contained in:
Miodrag Milanovic 2019-10-04 08:19:26 +02:00
parent 3b44084320
commit a7fbc8c3fe
2 changed files with 40 additions and 50 deletions
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40
tests/xilinx/adffs.v
View file

@ -45,43 +45,3 @@ module ndffnr
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3
);
dffs u_dffs (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnr u_ndffnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
endmodule

50
tests/xilinx/adffs.ys
View file

@ -1,14 +1,44 @@
read_verilog adffs.v
proc
flatten
equiv_opt -multiclock -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
design -save read
proc
hierarchy -top adff
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 2 t:FDCE
select -assert-count 1 t:FDRE
select -assert-count 1 t:FDRE_1
select -assert-count 1 t:FDCE
select -assert-none t:BUFG t:FDCE %% t:* %D
design -load read
proc
hierarchy -top adffn
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDCE
select -assert-count 1 t:LUT1
select -assert-count 2 t:LUT2
select -assert-none t:BUFG t:FDCE t:FDRE t:FDRE_1 t:LUT1 t:LUT2 %% t:* %D
select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
design -load read
proc
hierarchy -top dffs
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:LUT2
select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
design -load read
proc
hierarchy -top ndffnr
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE_1
select -assert-count 1 t:LUT2
select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D