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Add -assert
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@ -2,7 +2,7 @@ read_verilog counter.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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