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Add -assert

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Eddie Hung 2019-09-30 19:57:26 -07:00 committed by Miodrag Milanovic
parent 8422ad3e3a
commit 3b44084320
1 changed files with 1 additions and 1 deletions
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tests/xilinx/counter.ys
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@ -2,7 +2,7 @@ read_verilog counter.v
hierarchy -top top
proc
flatten
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module