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Code Activity
1475 commits 94 branches 52 tags 62 MiB
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57 commits

Author SHA1 Message Date
Clifford Wolf f53984795d Added support for non-standard """ macro bodies 2014-08-13 13:03:38 +02:00
Clifford Wolf d259abbda2 Added AST_MULTIRANGE (arrays with more than 1 dimension) 2014-08-06 15:52:54 +02:00
Clifford Wolf b5a3419ac2 Added support for non-standard "module mod_name(...);" syntax 2014-08-04 15:40:07 +02:00
Clifford Wolf 1202f7aa4b Renamed "stdcells.v" to "techmap.v" 2014-07-31 02:32:00 +02:00
Clifford Wolf 89c85cac41 Added links to some liberty files to README 2014-06-28 12:11:42 +02:00
Clifford Wolf b1b96d199f Added more calls to "hierarchy" to README file 2014-06-15 11:51:51 +02:00
Clifford Wolf 482d9208aa Added read_verilog -sv options, added support for bit, logic, 
allways_ff, always_comb, and always_latch
 2014-06-12 11:54:20 +02:00
Clifford Wolf 12a3c05229 Updated README 2014-04-18 10:19:46 +02:00
Clifford Wolf 94c1307c26 Added libs/minisat (copy of minisat git master) 2014-03-12 10:17:51 +01:00
Clifford Wolf 91704a7853 Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:24:24 +01:00
Clifford Wolf 078cecf9ea Updated todo items in README file 2014-02-05 01:59:30 +01:00
Clifford Wolf d06258f74f Added constant size expression support of sized constants 2014-02-01 13:50:23 +01:00
Clifford Wolf 1e2440e7ed Added note about SystemVerilog assert statement to README 2014-02-01 13:04:49 +01:00
Clifford Wolf aceab5fc08 Tiny change in example script in README 2014-01-29 11:11:10 +01:00
Clifford Wolf 09bd82db21 Fixes and other changes in README 2013-12-08 15:42:27 +01:00
Clifford Wolf 38e7fa6530 Tighter integration of ABC build 2013-11-27 09:08:35 +01:00
Clifford Wolf 620b7c900a Updated TODOs 2013-11-24 17:58:05 +01:00
Clifford Wolf 28093d9dd2 Added "top" attribute to mark top module in hierarchy 2013-11-24 05:03:43 +01:00
Clifford Wolf 295e352ba6 Renamed "placeholder" to "blackbox" 2013-11-22 15:01:12 +01:00
Clifford Wolf e4429c480e Enable {* .. *} feature per default (removes dependency to REJECT feature in flex) 2013-11-22 12:46:02 +01:00
Clifford Wolf 92035fb38e Implemented indexed part selects 2013-11-20 13:05:27 +01:00
Clifford Wolf ac2be2d892 Fixed name resolution of local tasks and functions in generate block 2013-11-20 11:05:58 +01:00
Clifford Wolf 19dba2561e Implemented part/bit select on memory read 2013-11-20 10:51:32 +01:00
Clifford Wolf d248419fe0 Updated TODOs in README file 2013-11-20 02:10:48 +01:00
Clifford Wolf e340532ce5 Added init= attribute for fpga-style reset values 2013-11-20 01:49:37 +01:00
Clifford Wolf 90300cbacc Removed done or obsolete TODO items 2013-11-07 12:55:09 +01:00
Clifford Wolf 1d34fd7608 Added support for "keep" attributes on wires 2013-11-05 15:52:29 +01:00
Clifford Wolf f912e029de Added roadmap to readme file 2013-11-02 13:19:04 +01:00
Clifford Wolf d78a9dfb37 Added paragraph to README file to avoid mycells.lib confusion 2013-10-31 11:15:00 +01:00
Clifford Wolf f024b19ed9 README file typo fix 2013-10-31 01:15:07 +01:00
Clifford Wolf cc7986a3e5 Some additions to the README file 2013-10-31 01:09:24 +01:00
Clifford Wolf 96e7abad48 Added iopadmap pass 2013-10-16 16:16:06 +02:00
Clifford Wolf a12d39bc86 Added recommended apt-get commands to README 2013-10-11 22:25:23 +02:00
Clifford Wolf 8b2f7792ba Updated TODO section in README 2013-08-01 20:02:15 +02:00
Clifford Wolf 3bb1996151 Added web site link to README 2013-07-21 15:04:37 +02:00
Clifford Wolf 3cd97a205f Added ast frontend refactoring to TODO 2013-07-11 19:31:57 +02:00
Clifford Wolf a4fd3cde8c Documentation updates 2013-07-04 14:17:25 +02:00
Clifford Wolf 6c8a424872 Added "make abc" and "make install-abc" 2013-06-08 23:48:19 +02:00
Clifford Wolf 7d0a274f12 Fixed README for new show command behavior (svg vs. ps) 2013-04-27 14:41:46 +02:00
Clifford Wolf 73fba5164f Implemented TCL support (only via -c option at the moment) 2013-03-28 12:26:17 +01:00
Clifford Wolf 7bfc7b61a8 Implemented proper handling of stub placeholder modules 2013-03-28 09:20:10 +01:00
Clifford Wolf 227520f94d Added nosync attribute and some async reset related fixes 2013-03-25 17:13:14 +01:00
Clifford Wolf 8cc1c87ab8 Reorganized TODOs 2013-03-24 11:23:54 +01:00
Clifford Wolf df9753d398 Added mem2reg option to verilog frontend 2013-03-24 11:13:32 +01:00
Johann Glaser 1d30c66a7f added a TODO 2013-03-18 22:06:53 +01:00
Johann Glaser 2192873daa added description of Makefile include files for build configuration 2013-03-18 19:26:35 +01:00
Clifford Wolf 71de666003 More TODOs in README 2013-03-18 15:05:15 +01:00
Johann Glaser bcae4aae6e corrected typos 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2013-03-17 09:05:14 +01:00
Clifford Wolf 8a6b0a3520 Added help messages to ilang and verilog frontends 2013-03-01 08:03:00 +01:00
Clifford Wolf 7fccad92f7 Added more help messages 2013-03-01 00:36:19 +01:00