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Implemented proper handling of stub placeholder modules

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Clifford Wolf 2013-03-28 09:20:10 +01:00
parent 98fcb5daa3
commit 7bfc7b61a8
7 changed files with 70 additions and 16 deletions
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@ -205,6 +205,12 @@ Verilog Attributes and non-standard features
temporary variable within an always block. This is mostly used internally
by yosys to synthesize verilog functions and access arrays.
- The "placeholder" attribute on modules is used to mark empty stub modules
that have the same ports as the real thing but do not contain information
on the internal configuration. This modules are only used by the synthesis
passes to identify input and output ports of cells. The verilog backend
also does not output placeholder modules on default.
- In addition to the (* ... *) attribute syntax, yosys supports
the non-standard {* ... *} attribute syntax to set default attributes
for everything that comes after the {* ... *} statement. (Reset