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Renamed "stdcells.v" to "techmap.v"

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Clifford Wolf 2014-07-31 02:32:00 +02:00
parent 6ca0c569d9
commit 1202f7aa4b
9 changed files with 15 additions and 12 deletions
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@ -304,8 +304,7 @@ Roadmap / Large-scale TODOs
- yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim
- Technology mapping for real-world applications
- Add bit-wise const-folding via cell parameters to techmap pass
- Rewrite current stdcells.v techmap rules (modular and clean)
- Rewrite current techmap.v rules (modular and clean)
- Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.)
- Implement SAT-based formal equivialence checker