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Fixed name resolution of local tasks and functions in generate block

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Clifford Wolf 2013-11-20 11:05:58 +01:00
parent 19dba2561e
commit ac2be2d892
2 changed files with 16 additions and 3 deletions
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@ -292,7 +292,6 @@ Roadmap / Large-scale TODOs
- yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim
- Missing Verilog-2005 features to be implemented soon:
- Fix corner cases with contextual name lookup
- Indexed part selects
- Technology mapping for real-world applications