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Added "top" attribute to mark top module in hierarchy

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Clifford Wolf 2013-11-24 05:03:43 +01:00
parent a4edecb0ca
commit 28093d9dd2
6 changed files with 63 additions and 3 deletions
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@ -262,6 +262,11 @@ Verilog Attributes and non-standard features
initialized "FPGA-style" with 'reg foo = val'. It can be used during synthesis
to add the necessary reset logic.
- The "top" attribute on a module marks this module as the top of the
design hierarchy. The "hierarchy" command sets this attribute when called
with "-top". Other commands, such as "flatten" and various backends
use this attribute to determine the top module.
- In addition to the (* ... *) attribute syntax, yosys supports
the non-standard {* ... *} attribute syntax to set default attributes
for everything that comes after the {* ... *} statement. (Reset